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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd new file mode 100644 index 000000000..a03dfa75d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd @@ -0,0 +1,52 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_11 is + +end entity inline_11; + + +---------------------------------------------------------------- + + +architecture test of inline_11 is + + signal sensitivity_list : bit := '0'; + +begin + + + -- code from book: + + -- make "sensitivity_list" roman italic + control_section : process ( sensitivity_list ) is + begin + null; + end process control_section; + + -- end of code from book + + stimulus : process is + begin + sensitivity_list <= '1' after 10 ns, '0' after 20 ns; + wait; + end process stimulus; + +end architecture test; + |