3 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/gna/issue642/ent.vhdl b/testsuite/gna/issue642/ent.vhdl
new file mode 100644
index 000000000..cae8c41cd
--- /dev/null
+++ b/testsuite/gna/issue642/ent.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+
+entity test is
+end entity;
+
+architecture a of test is
+	signal Combined : std_logic_vector(16 downto 0);
+	
+	signal SingleBit : std_logic;
+	signal Part1     : std_logic_vector(7 downto 0);
+	signal Part2     : std_logic_vector(7 downto 0);
+begin
+	(Part1, Part2)            <= Combined(Combined'left - 1 downto 0);  -- line 14: can't match 'part1' with type std_ulogic; can't match 'part2' with type std_ulogic
+	(SingleBit, Part1, Part2) <= Combined;                              -- line 15: can't match 'part1' with type std_ulogic; can't match 'part2' with type std_ulogic
+end architecture;
+
diff --git a/testsuite/gna/issue642/repro.vhdl b/testsuite/gna/issue642/repro.vhdl
new file mode 100644
index 000000000..e1288f47a
--- /dev/null
+++ b/testsuite/gna/issue642/repro.vhdl
@@ -0,0 +1,18 @@
+entity repro is
+end entity;
+
+architecture a of repro is
+	signal Combined : bit_vector(16 downto 0);
+	
+	signal SingleBit : bit;
+	signal Part1     : bit_vector(7 downto 0);
+	signal Part2     : bit_vector(7 downto 0);
+begin
+	process
+	begin
+	  (Part1, Part2)            <= Combined(Combined'left - 1 downto 0);
+	  (SingleBit, Part1, Part2) <= Combined;
+          wait;
+        end process;
+end architecture;
+
diff --git a/testsuite/gna/issue642/testsuite.sh b/testsuite/gna/issue642/testsuite.sh
new file mode 100755
index 000000000..e132bd00e
--- /dev/null
+++ b/testsuite/gna/issue642/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate repro
+
+analyze ent.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"