2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/issue191/repro.vhdl b/testsuite/gna/issue191/repro.vhdl
new file mode 100644
index 000000000..51b11c93c
--- /dev/null
+++ b/testsuite/gna/issue191/repro.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use      ieee.std_logic_1164.all;
+
+entity e is
+end entity;
+
+architecture a of e is
+  type t_rec is record
+    addr : std_logic_vector;
+  end record;
+  
+  function init_signals(bits : natural) return t_rec is
+    variable result : t_rec(addr(bits - 1 downto 0));
+  begin
+    result.addr   := (others => '0');
+    -- result.addr   := (result.addr'range => '0');  -- this works
+    return result;
+  end function;
+begin
+end architecture;
diff --git a/testsuite/gna/issue191/testsuite.sh b/testsuite/gna/issue191/testsuite.sh
new file mode 100755
index 000000000..ab5703a18
--- /dev/null
+++ b/testsuite/gna/issue191/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+# Cannot yet generate code.
+$GHDL -s --std=08 repro.vhdl
+
+clean
+
+echo "Test successful"