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Age
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*
netlist-disp_vhdl: add a separator between instances and signals.
Tristan Gingold
2022-07-26
1
-1
/
+1
*
vhdl-parse: set reference_terminal flag
Tristan Gingold
2022-07-26
1
-0
/
+1
*
testsuite/gna: add a test for #2138
Tristan Gingold
2022-07-25
2
-0
/
+40
*
vhdl-canon: handle conditional variable assignment. Fix #2138
Tristan Gingold
2022-07-25
1
-1
/
+16
*
simul: gather terminals
Tristan Gingold
2022-07-25
4
-3
/
+74
*
synth/elab-vhdl_values: add Value_Terminal
Tristan Gingold
2022-07-25
6
-4
/
+38
*
vhdl-nodes: add Get/Set_Reference_Terminal_Flag
Tristan Gingold
2022-07-25
6
-478
/
+541
*
synth-environment: fix memory crash. Fix #2139
Tristan Gingold
2022-07-25
1
-2
/
+8
*
dyn_tables,tables: add Reserve. For #2139
Tristan Gingold
2022-07-25
4
-5
/
+28
*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
7
-0
/
+3759
*
synth: add hook for dot attribute
Tristan Gingold
2022-07-24
3
-7
/
+17
*
pyGHDL/lsp: fix after renaming
Tristan Gingold
2022-07-22
1
-1
/
+1
*
testsuite/gna: add a test for #2136
Tristan Gingold
2022-07-21
3
-0
/
+70
*
vhdl: handle element attribute in declarations. Fix #2136
Tristan Gingold
2022-07-21
2
-12
/
+23
*
elab-vhdl_decls: elaborate dot attribute
Tristan Gingold
2022-07-21
3
-4
/
+14
*
vhdl-nodes: renaming.
Tristan Gingold
2022-07-21
23
-143
/
+145
*
elab-vhdl_decls: elaborate implicit signals
Tristan Gingold
2022-07-21
1
-2
/
+23
*
Makefile.in: allow build of ghdl_mcode with sundials enabled
Tristan Gingold
2022-07-21
2
-1
/
+26
*
synth-vhdl_expr: add hook for quantities
Tristan Gingold
2022-07-20
2
-11
/
+23
*
elab-vhdl_debug: handle signals in packages
Tristan Gingold
2022-07-20
1
-2
/
+8
*
grt: add analog_solver (work in progress)
Tristan Gingold
2022-07-20
4
-9
/
+197
*
grt: add real now variable.
Tristan Gingold
2022-07-20
4
-0
/
+19
*
ghdlsimul: simplify elaboration circuitery
Tristan Gingold
2022-07-20
1
-13
/
+0
*
elab-vhdl_context: add iterator for top-level packages
Tristan Gingold
2022-07-20
2
-0
/
+36
*
configure: add --with-sundials (preliminary work)
Tristan Gingold
2022-07-20
4
-1
/
+56
*
elab-vhdl_debug: disp fp64 values
Tristan Gingold
2022-07-20
4
-2
/
+10
*
testsuite/gna: add a test for #2134
Tristan Gingold
2022-07-16
3
-0
/
+61
*
vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134
Tristan Gingold
2022-07-16
1
-0
/
+2
*
vhdl: preliminary work to elaborat quantities
Tristan Gingold
2022-07-16
7
-2
/
+26
*
elab-vhdl_values: add Create_Value_Quantity
Tristan Gingold
2022-07-16
6
-2
/
+41
*
grt-types: add Mode_Above
Tristan Gingold
2022-07-16
4
-7
/
+15
*
vhdl: add Iir_Kinds_AMS_Signal_Attribute
Tristan Gingold
2022-07-16
5
-22
/
+38
*
vhdl-cannon: add Canon_Extract_Sensitivity_Break_Statement
Tristan Gingold
2022-07-16
2
-1
/
+16
*
netlists-inference: add (disabled) code to add a latch
Tristan Gingold
2022-07-16
1
-26
/
+103
*
testsuite/synth: add latch01
Tristan Gingold
2022-07-14
3
-0
/
+57
*
testsuite/synth: use standard functions for issue2125
Tristan Gingold
2022-07-14
1
-8
/
+2
*
synth: Display dlatch
Tristan Gingold
2022-07-14
3
-2
/
+9
*
Makefile.in: add dependency for local install of synth_gates.h
Tristan Gingold
2022-07-14
1
-1
/
+1
*
netlists: add d-latch
Tristan Gingold
2022-07-12
3
-2
/
+38
*
Fix access check failed from iir_kind_selected_element (#2132)
Michael Nolan
2022-07-12
1
-0
/
+1
*
testsuite/synth: add a test for #2125
Tristan Gingold
2022-07-11
6
-0
/
+152
*
testsuite/synth/dff02: do not run dff06 (creates a latch)
Tristan Gingold
2022-07-11
1
-1
/
+2
*
synth-environment: do inference during wire finalization
Tristan Gingold
2022-07-11
1
-13
/
+31
*
synth-environment: add Loc parameter to Add_Conc_Assign
Tristan Gingold
2022-07-11
3
-4
/
+13
*
netlists-inference: detect false loops only for variables. Fix #2125
Tristan Gingold
2022-07-11
1
-2
/
+3
*
testsuite/synth: add a test for #2113
Tristan Gingold
2022-07-08
2
-0
/
+66
*
netlists-disp_verilog: do not connect to null-range output. For #2113
Tristan Gingold
2022-07-08
1
-41
/
+47
*
vhdl-evaluation: explicitly compute integer_exp to handle overflow.
Tristan Gingold
2022-07-07
1
-2
/
+31
*
vhdl-evaluation: make overflow_literal non locally static.
Tristan Gingold
2022-07-07
2
-1
/
+6
*
netlists-disp_verilog: fix output for id_abs. For #2123
Tristan Gingold
2022-07-06
1
-1
/
+2
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