index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
vhdl synth: recognize more operators (add uns log).
Tristan Gingold
2019-09-02
4
-100
/
+157
*
revert "configure: fix setting abs_srcdir on MSYS2/MINGW" (#911) (#914)
1138-4EB
2019-09-02
1
-6
/
+5
*
Fix UPF (#905)
1138-4EB
2019-09-01
4
-5
/
+21
*
Fix configure (#911)
1138-4EB
2019-09-01
1
-216
/
+222
*
fix(configure): ignore line ending when comparing ghdl_version and libghdl_ve...
1138-4EB
2019-09-01
1
-1
/
+1
*
readme: fix refs to 'Building' (#909)
1138-4EB
2019-08-31
1
-3
/
+3
*
[doc] Update section 'Getting GHDL' (#906)
1138-4EB
2019-08-31
21
-425
/
+268
*
Merge pull request #907 from sharkcz/llvm-fix
tgingold
2019-08-31
1
-1
/
+1
|
\
|
*
fix llvm build with synth enabled
Dan HorĂ¡k
2019-08-31
1
-1
/
+1
|
/
*
synth: remove insert gate.
Tristan Gingold
2019-08-31
4
-70
/
+0
*
synth: improve synth_uresize.
Tristan Gingold
2019-08-31
3
-26
/
+50
*
synth: elab subprogram interfaces subtype
Tristan Gingold
2019-08-31
1
-2
/
+13
*
[PATCH] synth-environment: fix thinkos.
Tristan Gingold
2019-08-31
8
-15
/
+231
*
synth: add physical division (#904)
tgingold
2019-08-30
3
-1
/
+36
|
\
|
*
testsuite/synth: added test for the physical division
Martin Doerfelt
2019-08-30
2
-0
/
+25
|
*
synth: added division of physical type
Martin Doerfelt
2019-08-30
1
-1
/
+11
*
|
synth: add support for --synth on llvm, link with -lm.
Tristan Gingold
2019-08-30
2
-0
/
+6
*
|
synth: fix type elaboration of interfaces.
Tristan Gingold
2019-08-30
1
-2
/
+0
*
|
synth: remove unused const gates.
Tristan Gingold
2019-08-30
2
-13
/
+5
*
|
vhdl-annotations: ignore conditional variable assignment.
Tristan Gingold
2019-08-30
1
-1
/
+2
*
|
vhdl-annotate: handle shared anonymous subtype in interfaces.
Tristan Gingold
2019-08-30
1
-1
/
+4
*
|
synth: ignore report statement.
Tristan Gingold
2019-08-30
1
-0
/
+2
*
|
vhdl: recognize ieee.numeric_std std_match.
Tristan Gingold
2019-08-30
4
-196
/
+241
*
|
std_names: add std_match
Tristan Gingold
2019-08-30
2
-3
/
+5
*
|
vhdl: recognize 1164 condition operator, handle in synth.
Tristan Gingold
2019-08-30
5
-114
/
+137
*
|
synth: handle enumeration subtype in ranges.
Tristan Gingold
2019-08-30
1
-1
/
+2
*
|
synth: fix named association in record aggregate.
Tristan Gingold
2019-08-30
1
-1
/
+3
|
/
*
testsuite/synth: add testcase for records. Temporary disable stmt01
Tristan Gingold
2019-08-29
5
-0
/
+168
*
synth: add support for record types.
Tristan Gingold
2019-08-29
13
-82
/
+361
*
synth: Integer operators (#902)
marph91
2019-08-28
3
-0
/
+47
*
testsuite/synth: testcase for conditional signal assignment.
Tristan Gingold
2019-08-27
3
-0
/
+61
*
synth: support sequential conditional signal assignment.
Tristan Gingold
2019-08-27
2
-0
/
+3
*
testsuite/synth: add cases for assign.
Tristan Gingold
2019-08-27
4
-4
/
+62
*
testsuite/synth: add asgn01
Tristan Gingold
2019-08-27
5
-0
/
+124
*
synth: rework partial assignments
Tristan Gingold
2019-08-27
10
-182
/
+608
*
netlists-disp_vhdl: do not used literals for prefixes.
Tristan Gingold
2019-08-27
1
-12
/
+53
*
Makefile.in: Add .NOTPARALLEL. For #888
Tristan Gingold
2019-08-27
1
-0
/
+9
*
testsuite/synth: add fsm02 test.
Tristan Gingold
2019-08-27
5
-0
/
+181
*
ignore restrict in simulation (#897)
Pepijn de Vos
2019-08-20
2
-18
/
+17
*
synth: add support for constant exponentiation.
Tristan Gingold
2019-08-20
1
-0
/
+10
*
synth: set name to assert/assume gates.
Tristan Gingold
2019-08-20
4
-12
/
+44
*
netlist: fix minor pasto.
Tristan Gingold
2019-08-20
1
-1
/
+1
*
initial support for reduce and/or (#900)
Pepijn de Vos
2019-08-20
7
-6
/
+77
*
vhdl psl: fully scan PSL keywords in scanner.
Tristan Gingold
2019-08-20
7
-67
/
+148
*
vhdl-prints: handle architecture in verification unit hierarchical name.
Tristan Gingold
2019-08-20
1
-0
/
+7
*
testsuite/synth: add a test for previous commit.
Tristan Gingold
2019-08-20
2
-0
/
+13
*
vhdl: handle architecture in verification unit hierarchical name.
Tristan Gingold
2019-08-20
3
-13
/
+53
*
vhdl-prints: handle verification units.
Tristan Gingold
2019-08-20
1
-318
/
+354
*
testsuite/synth: add a test for assume directive in verification units.
Tristan Gingold
2019-08-20
2
-2
/
+11
*
vhdl: handle assume in verification units.
Tristan Gingold
2019-08-20
5
-1
/
+11
[next]