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* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-024-100/+157
* revert "configure: fix setting abs_srcdir on MSYS2/MINGW" (#911) (#914)1138-4EB2019-09-021-6/+5
* Fix UPF (#905)1138-4EB2019-09-014-5/+21
* Fix configure (#911)1138-4EB2019-09-011-216/+222
* fix(configure): ignore line ending when comparing ghdl_version and libghdl_ve...1138-4EB2019-09-011-1/+1
* readme: fix refs to 'Building' (#909)1138-4EB2019-08-311-3/+3
* [doc] Update section 'Getting GHDL' (#906)1138-4EB2019-08-3121-425/+268
* Merge pull request #907 from sharkcz/llvm-fixtgingold2019-08-311-1/+1
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| * fix llvm build with synth enabledDan Horák2019-08-311-1/+1
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* synth: remove insert gate.Tristan Gingold2019-08-314-70/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-313-26/+50
* synth: elab subprogram interfaces subtypeTristan Gingold2019-08-311-2/+13
* [PATCH] synth-environment: fix thinkos.Tristan Gingold2019-08-318-15/+231
* synth: add physical division (#904)tgingold2019-08-303-1/+36
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| * testsuite/synth: added test for the physical divisionMartin Doerfelt2019-08-302-0/+25
| * synth: added division of physical typeMartin Doerfelt2019-08-301-1/+11
* | synth: add support for --synth on llvm, link with -lm.Tristan Gingold2019-08-302-0/+6
* | synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
* | vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
* | vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
* | synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
* | vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-304-196/+241
* | std_names: add std_matchTristan Gingold2019-08-302-3/+5
* | vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-305-114/+137
* | synth: handle enumeration subtype in ranges.Tristan Gingold2019-08-301-1/+2
* | synth: fix named association in record aggregate.Tristan Gingold2019-08-301-1/+3
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* testsuite/synth: add testcase for records. Temporary disable stmt01Tristan Gingold2019-08-295-0/+168
* synth: add support for record types.Tristan Gingold2019-08-2913-82/+361
* synth: Integer operators (#902)marph912019-08-283-0/+47
* testsuite/synth: testcase for conditional signal assignment.Tristan Gingold2019-08-273-0/+61
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-272-0/+3
* testsuite/synth: add cases for assign.Tristan Gingold2019-08-274-4/+62
* testsuite/synth: add asgn01Tristan Gingold2019-08-275-0/+124
* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* Makefile.in: Add .NOTPARALLEL. For #888Tristan Gingold2019-08-271-0/+9
* testsuite/synth: add fsm02 test.Tristan Gingold2019-08-275-0/+181
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-207-6/+77
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-08-202-0/+13
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
* testsuite/synth: add a test for assume directive in verification units.Tristan Gingold2019-08-202-2/+11
* vhdl: handle assume in verification units.Tristan Gingold2019-08-205-1/+11
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