iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: improve support of out/inout variable parameters.	Tristan Gingold	2020-01-08	3	-9/+69
*	ci: fix gnat-gpl download URL (#1071)	eine	2020-01-08	1	-2/+2
*	fix btdi image names (#1070)	eine	2020-01-07	2	-2/+2
*	testsuite: add more tests for #1038	Tristan Gingold	2020-01-06	5	-0/+106
*	vhdl/translate: handle implicit record-record conversions.	Tristan Gingold	2020-01-06	1	-12/+1
*	vhdl/translate: minor refactoring.	Tristan Gingold	2020-01-06	2	-42/+43
*	vhdl: fix multiple reference in trans-chap3.	Tristan Gingold	2020-01-06	1	-2/+6
*	doc: add internals/ (WIP). Add a part for index.	Tristan Gingold	2020-01-06	4	-1/+159
*	testsuite: add a case for #1038	Tristan Gingold	2020-01-06	2	-0/+35
*	vhdl/translate: handle more partially constrained array subtypes. For #1038	Tristan Gingold	2020-01-06	3	-6/+10
*	Homogenise NEWS.md, conf.py cleanup (#1065)	eine	2020-01-03	3	-263/+107
*	testsuite: add cases for #1051	Tristan Gingold	2020-01-02	13	-0/+3855
*	vhdl: handle untranslated subtypes for record aggregates. Fix #1051	Tristan Gingold	2020-01-02	1	-3/+12
*	testsuite/synth: add a test for #1064	Tristan Gingold	2020-01-02	3	-0/+60
*	synth: handle scalar inout association for subprograms. Fix #1064	Tristan Gingold	2020-01-02	1	-0/+2
*	testsuite: complete test for #1063	Tristan Gingold	2020-01-02	1	-2/+6
*	vhdl: fix order of std_ulogic literals. For #1063	Tristan Gingold	2020-01-02	1	-3/+3
*	testsuite/synth: improve test for previous commit.	Tristan Gingold	2020-01-01	2	-4/+40
*	synth-disp_vhdl: handle conversion from signed integers.	Tristan Gingold	2020-01-01	1	-1/+5
*	synth: optimize integer mod for power of 2.	Tristan Gingold	2020-01-01	3	-0/+31
*	testsuite: add case for #1063	Tristan Gingold	2020-01-01	2	-0/+22
*	vhdl: evaluate std_logic matching equality. Fix #1063	Tristan Gingold	2020-01-01	2	-8/+54
*	testsuite/synth: add a case for #1062	Tristan Gingold	2020-01-01	3	-0/+47
*	vhdl: handle -gGEN=VAL for --synth. Fix #1062	Tristan Gingold	2020-01-01	6	-23/+213
*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2019-12-31	7	-0/+202
*	synth-inference: merge reset for sub-nets.	Tristan Gingold	2019-12-31	1	-1/+16
*	synth-environment: also optimize mux merge for sub-nets.	Tristan Gingold	2019-12-31	3	-1/+34
*	netlists-disp_vhdl: display iadff.	Tristan Gingold	2019-12-31	2	-7/+19
*	Add option for compiling Wishbone VIP for UVVM framework. (#1061)	m-kru	2019-12-31	1	-0/+6
*	testsuite/vests/vhdl-ams: update tests list.	Tristan Gingold	2019-12-31	1	-4/+4
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	10	-169/+225
*	testsuite/vests/vhdl-ams: update tests lists.	Tristan Gingold	2019-12-31	2	-40/+40
*	testsuite/vests/vhdl-ams: fix some tests.	Tristan Gingold	2019-12-31	2	-3/+3
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	17	-172/+484
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	12	-241/+539
*	ams-vhdl: add frequency function, minor fixes.	Tristan Gingold	2019-12-30	7	-186/+207
*	testsuite/vests/vhdl-ams: adjust tests lists.	Tristan Gingold	2019-12-30	2	-35/+35
*	testsuite/vests/vhdl-ams/ashenden: fix some tests.	Tristan Gingold	2019-12-30	2	-6/+4
*	ams-vhdl: handle record nature end name.	Tristan Gingold	2019-12-30	2	-0/+5
*	ams-vhdl: improve error recovery	Tristan Gingold	2019-12-30	6	-61/+92
*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	6	-90/+175
*	ams-vhdl: fix tree consistency for terminal declaration.	Tristan Gingold	2019-12-30	2	-3/+3
*	testsuite/vets/vhdl-ams: fix syntax.	Tristan Gingold	2019-12-30	14	-42/+42
*	ams-vhdl: correctly test and set staticness of dot/integ attributes.	Tristan Gingold	2019-12-30	1	-8/+7
*	ams-vhdl: print subnature declarations.	Tristan Gingold	2019-12-30	1	-1/+16
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	9	-466/+646
*	vhdl-ams: fix tree consistency for subnature declaration.	Tristan Gingold	2019-12-29	4	-9/+9
*	vhdl-ams: fix overload for simple simultaneous statement.	Tristan Gingold	2019-12-29	3	-4/+26
*	testsuite/synth: add test for #1058	Tristan Gingold	2019-12-29	3	-0/+61
*	synth: handle wire assigned to a static value. Fix #1058	Tristan Gingold	2019-12-29	3	-9/+104