iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	1	-189/+193
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	1	-181/+182
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-3/+3
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	1	-186/+187
*	vhdl: recognize sin and cos from math_real.	Tristan Gingold	2019-11-26	1	-178/+180
*	vhdl: recognize rising_edge/falling_edge.	Tristan Gingold	2019-11-06	1	-220/+221
*	Add names for formal input gates/attributes.	Tristan Gingold	2019-10-30	1	-167/+173
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-172/+174
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-2/+2
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-171/+172
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-171/+172
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	1	-171/+173
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	1	-171/+173
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	1	-171/+172
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-27/+27
*	vhdl: recognize PSL units reserved words.	Tristan Gingold	2019-08-16	1	-652/+657
*	python: regenerate files.	Tristan Gingold	2019-07-26	1	-201/+205
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-173/+179
*	Rework libghdl build/install procedure (#840)	1138-4EB	2019-06-17	1	-0/+747