iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	python: execute 'black'	eine	2020-08-23	1	-705/+394
*	vhdl: parse and analyze force/release signal assignment statements.	Tristan Gingold	2020-08-01	1	-189/+200
*	vhdl: replace base_type with parent_type in nodes	Tristan Gingold	2020-07-22	1	-3/+3
*	vhdl: create default configuration for a vunit. Fix #1372	Tristan Gingold	2020-06-15	1	-277/+281
*	Synthesis of PSL prev function.	Tristan Gingold	2020-06-02	1	-3/+3
*	vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662	Tristan Gingold	2020-06-02	1	-0/+12
*	types: introduce Direction_Type, which replaces Iir_Direction.	Tristan Gingold	2020-04-20	1	-9/+9
*	vhdl: add scalar_size. Size of scalar types is computed during analysis.	Tristan Gingold	2020-04-06	1	-97/+104
*	synthesis: add option --vendor-library= for synthesis.	Tristan Gingold	2020-03-10	1	-141/+145
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-70/+78
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	1	-206/+210
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	1	-287/+375
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	1	-13/+17
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	1	-95/+103
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-3/+3
*	synth: handle verification units.	Tristan Gingold	2019-08-20	1	-245/+249
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-245/+257
*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	1	-272/+268
*	Rework libghdl build/install procedure (#840)	1138-4EB	2019-06-17	1	-0/+1435