| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: handle more operations from synsopsys packages. | Tristan Gingold | 2020-03-14 | 1 | -77/+79 |
| * | std_names: add *_reduce names. | Tristan Gingold | 2020-03-13 | 1 | -183/+189 |
| * | vhdl: recognize more std_logic_arith operations. | Tristan Gingold | 2020-03-13 | 1 | -0/+32 |
| * | vhdl-ieee-std_logic_arith: recognize more conversions. | Tristan Gingold | 2020-03-11 | 2 | -183/+188 |
| * | vhdl: recognize mod/rem operators. | Tristan Gingold | 2020-03-10 | 1 | -162/+174 |
| * | synthesis: add option --vendor-library= for synthesis. | Tristan Gingold | 2020-03-10 | 3 | -169/+179 |
| * | python: update setup.py to install ghdl-ls | Tristan Gingold | 2020-03-09 | 2 | -10/+35 |
| * | Import vhdl_langserver from ghdl-language-server | Tristan Gingold | 2020-03-09 | 11 | -0/+1510 |
| * | [PATCH] Add names for synopsys packages. | Tristan Gingold | 2020-03-03 | 2 | -224/+228 |
| * | Set version to 1.0-dev | Tristan Gingold | 2020-02-28 | 1 | -1/+1 |
| * | Release 0.37 | Tristan Gingold | 2020-02-28 | 1 | -1/+1 |
| * | vhdl: recognize conversion functions from std_logic_1164 | Tristan Gingold | 2020-02-18 | 2 | -405/+415 |
| * | synth: handle some rotation and shifts. Fix #1077 | Tristan Gingold | 2020-01-30 | 1 | -205/+209 |
| * | synth: handle matching comparisons. Fix #1109 | Tristan Gingold | 2020-01-24 | 1 | -90/+126 |
| * | synth: add id_abs gate. For #1101 | Tristan Gingold | 2020-01-20 | 1 | -71/+72 |
| * | synth: handle more signed operations. For #1101 | Tristan Gingold | 2020-01-19 | 1 | -140/+144 |
| * | vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077 | Tristan Gingold | 2020-01-11 | 1 | -77/+85 |
| * | synth: handle ieee.math_real.round Fix #1075 | Tristan Gingold | 2020-01-10 | 3 | -235/+238 |
| * | ams-vhdl: add support for 'delayed for quantity. | Tristan Gingold | 2019-12-31 | 1 | -25/+28 |
| * | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 3 | -101/+126 |
| * | ams-vhdl: add simultaneous null statement. | Tristan Gingold | 2019-12-30 | 1 | -86/+90 |
| * | ams-vhdl: add frequency function, minor fixes. | Tristan Gingold | 2019-12-30 | 1 | -180/+181 |
| * | ams-vhdl: check nature for record natures and terminals. | Tristan Gingold | 2019-12-30 | 2 | -235/+249 |
| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 3 | -741/+1004 |
| * | vhdl: add Has_Delay_Machanism for optional 'inertial' printing. | Tristan Gingold | 2019-12-26 | 2 | -13/+21 |
| * | vhdl: recognize ieee.std_logic_1164.is_x. | Tristan Gingold | 2019-12-24 | 2 | -345/+348 |
| * | vhdl: recognize sin and cos from math_real. | Tristan Gingold | 2019-11-26 | 2 | -225/+229 |
| * | synth: preliminary work to support intrinsic procedures. | Tristan Gingold | 2019-11-14 | 1 | -172/+175 |
| * | files_map-editor: add Copy_Source_File. | Tristan Gingold | 2019-11-06 | 1 | -0/+2 |
| * | files_map: add Discard_Source_File, Free_Source_File, | Tristan Gingold | 2019-11-06 | 1 | -0/+3 |
| * | files_map-editor: turn Replace_Text to a function. | Tristan Gingold | 2019-11-06 | 1 | -0/+4 |
| * | vhdl: recognize rising_edge/falling_edge. | Tristan Gingold | 2019-11-06 | 2 | -375/+378 |
| * | Add names for formal input gates/attributes. | Tristan Gingold | 2019-10-30 | 1 | -167/+173 |
| * | vhdl: recognize std_logic_unsigned.conv_integer. | Tristan Gingold | 2019-10-13 | 1 | -18/+19 |
| * | vhdl: recognize conv_integer functions from std_logic_arith. | Tristan Gingold | 2019-10-11 | 2 | -172/+178 |
| * | vhdl: recognize std_logic_signed package (from synopsys). | Tristan Gingold | 2019-10-11 | 2 | -6/+16 |
| * | vhdl: recognize minus from std_logic_unsigned | Tristan Gingold | 2019-10-11 | 1 | -22/+27 |
| * | vhdl: recognize conv_unsigned from ieee.std_logic_arith. | Tristan Gingold | 2019-10-10 | 2 | -171/+176 |
| * | synth: handle package bodies. | Tristan Gingold | 2019-10-07 | 2 | -302/+304 |
| * | vhdl: recognize div operators. | Tristan Gingold | 2019-09-30 | 1 | -90/+96 |
| * | vhdl: recognize rotate functions. | Tristan Gingold | 2019-09-22 | 2 | -217/+223 |
| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 2 | -95/+115 |
| * | vhdl: recognize numeric_std shift_left. | Tristan Gingold | 2019-09-11 | 2 | -217/+223 |
| * | vhdl: recognize numeric_std mul. | Tristan Gingold | 2019-09-07 | 1 | -82/+88 |
| * | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 2 | -5/+5 |
| * | vhdl synth: recognize more operators (add uns log). | Tristan Gingold | 2019-09-02 | 1 | -91/+95 |
| * | vhdl: recognize ieee.numeric_std std_match. | Tristan Gingold | 2019-08-30 | 2 | -196/+202 |
| * | vhdl: recognize 1164 condition operator, handle in synth. | Tristan Gingold | 2019-08-30 | 2 | -109/+118 |
| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 2 | -245/+253 |
| * | vhdl: parse verification unit (WIP). | Tristan Gingold | 2019-08-17 | 1 | -242/+243 |
