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* simul: handle psl assume directivesTristan Gingold2023-01-111-0/+2
* simul: enable all debug features during elaborationTristan Gingold2023-01-101-4/+0
* synth-vhdl_aggr: optimize common aggregateTristan Gingold2023-01-101-6/+8
* synth: always create shared variablesTristan Gingold2023-01-091-21/+2
* simul: handle function calls in sensitivity compute.Tristan Gingold2023-01-091-0/+6
* simul: improve error recovery during elaborationTristan Gingold2023-01-091-3/+12
* simul: handle PSL coverTristan Gingold2023-01-091-2/+5
* synth: introduce type_array_unboundedTristan Gingold2023-01-031-0/+1
* simul: skip psl default clock in declarationsTristan Gingold2023-01-031-0/+1
* synth: fix to_string for characterTristan Gingold2023-01-021-0/+3
* synth: elaborate case generate statementsTristan Gingold2023-01-011-1/+2
* simul: handle nested packagesTristan Gingold2023-01-011-1/+5
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-1/+1
* simul: handle transaction attributeTristan Gingold2022-12-261-0/+9
* vhdl-sem_inst: add instantiate_interface_package_declarationTristan Gingold2022-12-181-0/+4
* vhdl: fix some compiler warningsTristan Gingold2022-11-081-2/+0
* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
* simul: handle delayed attributeTristan Gingold2022-10-141-0/+11
* simul-vhdl_elab: fix crash on association with implicit signalsTristan Gingold2022-10-131-1/+4
* simul: recompute object alias offsetsTristan Gingold2022-10-061-1/+14
* simul: fix signal attribute or guard as actual in connectionsTristan Gingold2022-10-061-10/+12
* simul: handle stable attributeTristan Gingold2022-09-301-0/+11
* simul: handle quiet attributeTristan Gingold2022-09-291-0/+29
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-291-66/+51
* simul-vhdl_elab: avoid a crash for null-range signalsTristan Gingold2022-09-261-10/+14
* synth: handle attributes in configurationsTristan Gingold2022-09-261-1/+3
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-251-29/+80
* synth: ignore groups and group templatesTristan Gingold2022-09-251-1/+3
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-251-3/+7
* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
* simul: fix resolved associationTristan Gingold2022-09-171-1/+2
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-171-3/+2
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-171-1/+1
* synth: handle protected types in subprogramsTristan Gingold2022-09-171-31/+3
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-13/+5
* simul: improve error handling during elaborationTristan Gingold2022-09-161-0/+1
* simul: add support for protected objectsTristan Gingold2022-09-081-1/+53
* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
* synth: handle generics in blocksTristan Gingold2022-09-061-2/+18
* synth: use areapoolsTristan Gingold2022-09-021-4/+32
* simul: detect multiple drivers for unresolved signalsTristan Gingold2022-09-021-8/+93
* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-251-1/+2
* simul: handle conversions and associations with constantsTristan Gingold2022-08-241-27/+26
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-231-0/+35
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-231-10/+76
* simul: handle individual associationsTristan Gingold2022-08-171-2/+7
* simul: add create_connectsTristan Gingold2022-08-171-37/+38
* simul: create terminals (WIP)Tristan Gingold2022-08-171-1/+2
* simul: gather terminalsTristan Gingold2022-07-251-0/+29
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-241-0/+677
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