| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: adjust for iir_kind_package_instantiation_body | Tristan Gingold | 2023-03-27 | 1 | -0/+2 |
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| * | synth: always create shared variables | Tristan Gingold | 2023-01-09 | 1 | -6/+12 |
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| * | simul: handle nested packages | Tristan Gingold | 2023-01-01 | 1 | -0/+10 |
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| * | synth: avoid extra conversion during alias elaboration | Tristan Gingold | 2022-10-14 | 1 | -6/+4 |
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| * | simul: handle quiet attribute | Tristan Gingold | 2022-09-29 | 1 | -2/+1 |
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| * | synth: ignore groups and group templates | Tristan Gingold | 2022-09-25 | 1 | -0/+7 |
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| * | simul: use synth_declarations for processes and procedures | Tristan Gingold | 2022-09-17 | 1 | -13/+0 |
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| * | synth: factorize code (reuse synth_constant_declaration) | Tristan Gingold | 2022-09-17 | 1 | -64/+5 |
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| * | synth: handle incomplete types | Tristan Gingold | 2022-09-17 | 1 | -1/+11 |
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| * | synth: preliminary work to factorize code | Tristan Gingold | 2022-09-16 | 1 | -3/+1 |
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| * | synth: improve handling of top-level interfaces subtype | Tristan Gingold | 2022-09-11 | 1 | -0/+2 |
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| * | synth: fix and add checks for memory management. | Tristan Gingold | 2022-09-10 | 1 | -3/+1 |
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| * | simul: add support for protected objects | Tristan Gingold | 2022-09-08 | 1 | -7/+2 |
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| * | elab-vhdl_values: factorize code | Tristan Gingold | 2022-09-07 | 1 | -1/+1 |
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| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 1 | -2/+45 |
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| * | elab: add default value to ports | Tristan Gingold | 2022-08-23 | 1 | -9/+16 |
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| * | elab-vhdl_expr: factorize code | Tristan Gingold | 2022-08-19 | 1 | -5/+10 |
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| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+28 |
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| * | elab-vhdl_decls: elaborate dot attribute | Tristan Gingold | 2022-07-21 | 1 | -0/+13 |
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| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 1 | -3/+3 |
| | | | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities. | ||||
| * | elab-vhdl_decls: elaborate implicit signals | Tristan Gingold | 2022-07-21 | 1 | -2/+23 |
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| * | vhdl: preliminary work to elaborat quantities | Tristan Gingold | 2022-07-16 | 1 | -0/+13 |
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| * | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 1 | -8/+12 |
| | | | | | Fix #2085 | ||||
| * | synth: handle suspend state declaration and statement | Tristan Gingold | 2022-05-27 | 1 | -0/+7 |
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| * | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 1 | -5/+13 |
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| * | synth: handle shared variable without default value. | Tristan Gingold | 2022-04-04 | 1 | -1/+1 |
| | | | | | For #2023 | ||||
| * | synth: handle package instantiation in declarations. Fix #1938 | Tristan Gingold | 2022-01-03 | 1 | -0/+3 |
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| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+361 |
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index : iCE40/ghdl | |
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