| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | netlists-disp_verilog: fix name for memory initialization | Tristan Gingold | 2021-09-28 | 1 | -3/+4 |
| * | netlists-disp_verilog: fix output of parameter assignments. Fix #1866 | Tristan Gingold | 2021-09-15 | 1 | -12/+12 |
| * | netlists-disp_verilog.adb: add 'parameter' before parameters declaration | Tristan Gingold | 2021-09-15 | 1 | -1/+1 |
| * | synth/netlists-disp_verilog: fix output of parameter values. For #1866 | Tristan Gingold | 2021-09-15 | 1 | -1/+13 |
| * | netlists-disp_verilog: handle initial value for idff and isignal | Tristan Gingold | 2021-08-28 | 1 | -8/+18 |
| * | netlists-disp_verilog: fix handling of unconnected port | Tristan Gingold | 2021-08-26 | 1 | -3/+1 |
| * | synth: reuse signal name while creating memories. Fix #1838 | Tristan Gingold | 2021-08-25 | 1 | -4/+4 |
| * | netlists-disp_verilog: fix display of constants | Tristan Gingold | 2021-05-07 | 1 | -10/+20 |
| * | netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract. | Tristan Gingold | 2021-05-04 | 1 | -74/+14 |
| * | synth: add verilog output | Tristan Gingold | 2021-04-28 | 1 | -0/+1396 |
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index : iCE40/ghdl | |
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