| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: rewrite cleanup pass. | Tristan Gingold | 2019-10-10 | 1 | -7/+0 |
| * | synth: fold addition on constant nets. | Tristan Gingold | 2019-09-17 | 1 | -0/+1 |
| * | synth: minor refactoring about const gates. | Tristan Gingold | 2019-09-15 | 1 | -1/+1 |
| * | synth: rework partial assignments | Tristan Gingold | 2019-08-27 | 1 | -0/+7 |
| * | add port width utility function for yosys (#876) | Pepijn de Vos | 2019-07-21 | 1 | -0/+3 |
| * | synth: disp_vhdl: merge literals. | Tristan Gingold | 2019-06-28 | 1 | -0/+3 |
| * | synth: Move get_input_net to netlists.utils. | Tristan Gingold | 2019-06-28 | 1 | -0/+2 |
| * | synth: defer gates removal after at end of entity synthesis. | Tristan Gingold | 2017-02-15 | 1 | -0/+6 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+44 |
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index : iCE40/ghdl | |
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