iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: preliminary work to export module parameters.	Tristan Gingold	2020-03-31	1	-0/+110
*	synth-disp_vhdl: do not wrap inout ports. For #1166	Tristan Gingold	2020-03-22	1	-1/+3
*	synth: handle reuse of inferred dff in the same process.	Tristan Gingold	2020-03-22	1	-0/+1
*	synth: rework (again) memory inference.	Tristan Gingold	2020-02-10	1	-11/+10
*	netlists: use a mark and sweep cleanup.	Tristan Gingold	2020-01-15	1	-0/+1
*	netlists: remove port API (make it easier to interface).	Tristan Gingold	2019-11-28	1	-29/+52
*	netlists: remove port_inout.	Tristan Gingold	2019-11-28	1	-1/+1
*	synth: rework the sname API.	Tristan Gingold	2019-11-28	1	-14/+7
*	synth/netlists: remove unused function.	Tristan Gingold	2019-11-28	1	-7/+0
*	netlists: add 2 flags per instance, including a mark flag.	Tristan Gingold	2019-11-11	1	-0/+18
*	netlists: add remove_instance.	Tristan Gingold	2019-10-16	1	-0/+32
*	netlists: give a name to the free module.	Tristan Gingold	2019-10-10	1	-2/+4
*	synth: rewrite cleanup pass.	Tristan Gingold	2019-10-10	1	-0/+40
*	netlists: remove get_parent renaming for input.	Tristan Gingold	2019-10-06	1	-1/+1
*	netlists: remove renaming of Get_Parent for Net.	Tristan Gingold	2019-10-06	1	-1/+1
*	netlists: remove get_name renaming for modules.	Tristan Gingold	2019-10-06	1	-1/+1
*	synth: allow entities with no ports.	Tristan Gingold	2019-09-25	1	-1/+0
*	synth-inference: detect false loop.	Tristan Gingold	2019-09-17	1	-0/+5
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-5/+14
*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	1	-0/+6
*	synth: remove bounds (unused) for ports.	Tristan Gingold	2019-07-22	1	-3/+1
*	synth: add concatn gate	Tristan Gingold	2019-07-19	1	-18/+49
*	synth: display instances in reverse order.	Tristan Gingold	2019-07-10	1	-5/+13
*	synth: Move get_input_net to netlists.utils.	Tristan Gingold	2019-06-28	1	-5/+0
*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	1	-0/+5
*	synth: defer gates removal after at end of entity synthesis.	Tristan Gingold	2017-02-15	1	-22/+16
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+812