iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	update license headers	umarcor	2021-02-05	1	-5/+3
*	synth: always finalize declarations. Fix #1591	Tristan Gingold	2021-01-13	1	-0/+3
*	synth: create abstractions for Pval (from synth-insts to synth-decls)	Tristan Gingold	2020-05-20	1	-0/+7
*	synth: handle vhdl-08 ports. Fix ghdl/ghdl-yosys-plugin#111	Tristan Gingold	2020-05-07	1	-0/+3
*	synth: revert a previous commit: remove the En parameter.	Tristan Gingold	2020-05-06	1	-9/+4
*	synth: propagate enable condition to expressions. For #1273	Tristan Gingold	2020-05-01	1	-4/+9
*	synth: extract synth.objtypes from synth.values.	Tristan Gingold	2020-04-09	1	-1/+1
*	synth: handle multiple constant declarations. Fix #1172	Tristan Gingold	2020-03-23	1	-2/+4
*	synth: preliminary work for package instantiation. For #1159	Tristan Gingold	2020-03-23	1	-0/+8
*	synth: initial support of access types.	Tristan Gingold	2019-11-17	1	-0/+2
*	synth: add support for file declarations.	Tristan Gingold	2019-11-13	1	-0/+1
*	synth: add support for declarations in vunits.	Tristan Gingold	2019-10-23	1	-0/+3
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-0/+2
*	synth: preliminary support for user packages.	Tristan Gingold	2019-10-07	1	-0/+3
*	synth: finalize declarations and free wires.	Tristan Gingold	2019-09-27	1	-0/+4
*	synth: rework type for expression.	Tristan Gingold	2019-09-25	1	-0/+4
*	synth: initialize subprogram variables.	Tristan Gingold	2019-09-13	1	-3/+3
*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	1	-0/+7
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-0/+4
*	synth: handle enumerated types.	Tristan Gingold	2019-06-12	1	-2/+2
*	synth: add comments and refactoring.	Tristan Gingold	2019-06-07	1	-1/+1
*	vhdl: rename iirs to vhdl.nodes	Tristan Gingold	2019-05-05	1	-1/+1
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+28