| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 1 | -1/+2 |
| * | synth: handle integers for displaying vhdl ports. | Tristan Gingold | 2019-08-16 | 1 | -0/+10 |
| * | add synthesis support for logic operators on numeric types (#893) | Pepijn de Vos | 2019-08-15 | 1 | -0/+11 |
| * | synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr. | Tristan Gingold | 2019-08-08 | 1 | -3/+12 |
| * | synth: handle more conversions in disp_vhdl | Tristan Gingold | 2019-07-29 | 1 | -1/+44 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -0/+231 |
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index : iCE40/ghdl | |
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