| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: improve debugging routines. | Tristan Gingold | 2020-05-04 | 1 | -11/+20 |
| * | synth: use tri_state_type for seq_assign_value. | Tristan Gingold | 2020-05-04 | 1 | -5/+8 |
| * | synth-environment-debug: improve the debug code for wires. | Tristan Gingold | 2020-04-14 | 1 | -7/+14 |
| * | synth: refactoring to store static values in wires. | Tristan Gingold | 2020-04-09 | 1 | -1/+5 |
| * | netlists-dump: indent output. | Tristan Gingold | 2019-11-05 | 1 | -2/+2 |
| * | netlists: remove renaming of Get_Parent for Net. | Tristan Gingold | 2019-10-06 | 1 | -2/+2 |
| * | synth-environment-debug: add dump_partial_assign. | Tristan Gingold | 2019-10-01 | 1 | -10/+17 |
| * | synth-environment-debug: improve. | Tristan Gingold | 2019-09-26 | 1 | -1/+2 |
| * | synth: rework partial assignments | Tristan Gingold | 2019-08-27 | 1 | -4/+16 |
| * | synth: add a debug procedure. | Tristan Gingold | 2019-08-02 | 1 | -0/+21 |
| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 1 | -8/+8 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+76 |
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index : iCE40/ghdl | |
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