iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	synth: abstract of Merge_Assigns.	Tristan Gingold	2019-09-06	1	-56/+111
*	synth: add netlists.concats	Tristan Gingold	2019-09-05	1	-31/+7
*	[PATCH] synth-environment: fix thinkos.	Tristan Gingold	2019-08-31	1	-14/+57
*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-4/+0
*	synth: rework partial assignments	Tristan Gingold	2019-08-27	1	-130/+488
*	synth: improve error message for multiple assignments.	Tristan Gingold	2019-08-02	1	-4/+20
*	synth: handle partial assignments in a process (WIP).	Tristan Gingold	2019-08-01	1	-18/+75
*	synth: refactoring in inference/environment.	Tristan Gingold	2019-08-01	1	-1/+8
*	synth: refactor inference, add comment, strengthen check.	Tristan Gingold	2019-08-01	1	-12/+18
*	synth: add concatn gate	Tristan Gingold	2019-07-19	1	-1/+10
*	synth: finalize concurrent assignments (WIP).	Tristan Gingold	2019-07-19	1	-23/+274
*	synth: make type Wire_Id_Record private.	Tristan Gingold	2019-07-17	1	-0/+29
*	synth: renaming of Assign to Seq_Assign.	Tristan Gingold	2019-07-17	1	-50/+52
*	synth: add comments.	Tristan Gingold	2019-07-17	1	-0/+1
*	synth: add comments.	Tristan Gingold	2019-07-15	1	-6/+10
*	synth-environement: add comments.	Tristan Gingold	2019-07-08	1	-0/+3
*	synth: support async reset in inference.	Tristan Gingold	2019-04-16	1	-0/+3
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+334