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Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious
latch detection.
For #2086
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Simplifies memory extraction
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This optimization is important for the control wires to avoid false paths.
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For #1069
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Fix tgingold/ghdlsynth-beta#93
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Preliminary work to support multi-clock memories.
Strengthen and fix fallout of Check_Connected.
Rename synth.inference to netlists.inference.
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