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* is_tribuf_net: refineTristan Gingold2023-04-161-3/+10
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* synth-environment.adb: fix warningTristan Gingold2022-11-051-1/+0
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* synth: rework memory inference. Fix #2232Tristan Gingold2022-11-051-14/+28
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* synth-environment: fix memory crash. Fix #2139Tristan Gingold2022-07-251-2/+8
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* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
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* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-111-2/+6
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* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
| | | | | | Do not transform a Dyn_Insert into a Dyn_Insert_En, to avoid spurious latch detection. For #2086
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-281-0/+12
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* synth: improve result of is_positiveTristan Gingold2021-08-291-5/+0
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-281-0/+98
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* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-211-0/+27
| | | | Simplifies memory extraction
* synth: add a gate on an optimization to simplify memory handling.Tristan Gingold2021-06-171-6/+12
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* netlists-memories: strengthen dyn_extract mux reduction. Fix #1781Tristan Gingold2021-06-161-0/+1
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* synth: minor fixesTristan Gingold2021-06-151-1/+1
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* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-071-1/+20
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* synth: use a generic version of synth-environment.Tristan Gingold2021-04-271-263/+45
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* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-161-7/+7
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* update license headersumarcor2021-02-051-5/+3
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* synth: always finalize declarations. Fix #1591Tristan Gingold2021-01-131-9/+20
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* synth: improve diagnostic for multiple assignment. Fix #1428Tristan Gingold2020-08-261-8/+176
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* synth: push extract on mux2 for inference. For #1421Tristan Gingold2020-08-061-17/+18
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* synth-environment: allow multiple assignments from instance portsTristan Gingold2020-07-021-17/+16
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* netlists-memories: cleanup.Tristan Gingold2020-05-291-6/+0
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* netlists: rework clock handling in memories.Tristan Gingold2020-05-291-0/+4
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* synth-environment: fix handling of static values in case statements. Fix #1319Tristan Gingold2020-05-181-2/+2
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* synth: handle inout ports with default values. For #1312Tristan Gingold2020-05-161-1/+5
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* synth: add support for sequential assertions. Fix #1273Tristan Gingold2020-05-061-45/+131
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* synth: add comments.Tristan Gingold2020-05-041-2/+0
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* synth: reduce use of global context.Tristan Gingold2020-05-041-9/+10
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* synth: improve debugging routines.Tristan Gingold2020-05-041-3/+3
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* synth: minor refactoring for clean-up.Tristan Gingold2020-05-041-24/+45
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* synth: partial refactoring to improve handling of controls in case statements.Tristan Gingold2020-05-041-65/+98
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* synth: use tri_state_type for seq_assign_value.Tristan Gingold2020-05-041-58/+63
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* synth-environment: minor change to ease debugging.Tristan Gingold2020-05-041-2/+5
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* synth: use static values for control nets when possible.Tristan Gingold2020-05-021-25/+95
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* synth: add many calls to set_locationTristan Gingold2020-04-261-2/+4
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* synth-environment: add an optimization. Fix #1258Tristan Gingold2020-04-241-0/+4
| | | | This optimization is important for the control wires to avoid false paths.
* synth: insert resolver to handle multiple drivers to a signal. Fix #1238Tristan Gingold2020-04-221-3/+52
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* synth: do not try to do inference on unused nets. Fix #1225Tristan Gingold2020-04-141-1/+5
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* synth: refactoring to store static values in wires.Tristan Gingold2020-04-091-111/+195
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* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-12/+75
| | | | For #1069
* synth-environment: fix incorrect memory access.Tristan Gingold2020-03-251-2/+6
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* synth-environment: simplify code.Tristan Gingold2020-03-251-9/+5
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* synth: handle reuse of inferred dff in the same process.Tristan Gingold2020-03-221-25/+60
| | | | Fix tgingold/ghdlsynth-beta#93
* synth-environment: keep order of seq_assign in phi nodes.Tristan Gingold2020-03-211-5/+11
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* synth: refactoring inference (WIP).Tristan Gingold2020-03-151-32/+69
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* synth-environment: handle unassigned outputs.Tristan Gingold2020-02-181-6/+8
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* synth: rework (again) memory inference.Tristan Gingold2020-02-101-7/+25
| | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
* synth: improve support of out/inout variable parameters.Tristan Gingold2020-01-081-0/+2
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* synth-environment: also optimize mux merge for sub-nets.Tristan Gingold2019-12-311-1/+1
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