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* synth: refactoring to store static values in wires.Tristan Gingold2020-04-091-2/+2
* synth: extract synth.objtypes from synth.values.Tristan Gingold2020-04-091-0/+1
* synth: add value_memory and use it to store objects value.Tristan Gingold2020-04-061-3/+4
* synth: more cleanup (and use of valtyp).Tristan Gingold2020-04-021-3/+11
* synth: rework - use valtyp for expressions.Tristan Gingold2020-04-021-8/+7
* synth: handle user-defined operator call.Tristan Gingold2020-03-081-0/+6
* synth: rework static calls and loops. Fix #1034.Tristan Gingold2019-11-271-30/+49
* synth: revert patch on synth_subprogram_association.Tristan Gingold2019-10-061-2/+0
* synth: handle subtypes in components. Fix #970Tristan Gingold2019-10-061-0/+2
* synth: factorize code to read memories.Tristan Gingold2019-10-041-0/+7
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-0/+2
* synth: refactoring of alias (allow alias of anything).Tristan Gingold2019-09-301-1/+1
* synth: finalize declarations and free wires.Tristan Gingold2019-09-271-0/+3
* synth: handle exit/next statements.Tristan Gingold2019-09-221-0/+28
* synth: remove T_En from Seq_Context.Tristan Gingold2019-09-211-9/+1
* synth: improve support of return statement.Tristan Gingold2019-09-111-4/+7
* synth: introduce Seq_Context.Tristan Gingold2019-09-111-0/+25
* synth: move synth_user_function_call to synth-stmts.Tristan Gingold2019-09-111-2/+2
* synth: handle alias (WIP, read only).Tristan Gingold2019-09-111-0/+7
* synth: handle verification units.Tristan Gingold2019-08-201-0/+3
* synth: handle subtype conversions.Tristan Gingold2019-08-051-1/+2
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-281-2/+2
* synth: handle choices by range in aggregates.Tristan Gingold2019-07-151-0/+6
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-0/+5
* synth: handle simple user function calls.Tristan Gingold2019-07-061-0/+3
* synth: handle more predefined functions.Tristan Gingold2019-06-231-0/+5
* synth-stmts: handle enumeration type in case, renaming.Tristan Gingold2019-06-131-1/+1
* synth: support conditional signal assignments.Tristan Gingold2019-06-081-1/+2
* synth: add comments and refactoring.Tristan Gingold2019-06-071-1/+1
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+27