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* netlists-disp_vhdl: handle const_SB32Tristan Gingold2019-10-091-1/+2
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* synth-environment: fix a thinko.Tristan Gingold2019-10-091-1/+2
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* synth: improve support of procedure calls.Tristan Gingold2019-10-081-20/+25
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* synth: handle read-only aliases. Fix #973Tristan Gingold2019-10-081-1/+9
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* synth-context: fix encoding of discrete in aggregateTristan Gingold2019-10-081-1/+1
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* synth-disp_vhdl: fix incorrect code for record of widthTristan Gingold2019-10-081-1/+3
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* synth: fix mul sgn sgn width.Tristan Gingold2019-10-082-8/+9
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* synth: fix incorrect order for concat.Tristan Gingold2019-10-082-3/+6
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* synth-disp_vhdl: handle array/record of 1 element.Tristan Gingold2019-10-081-3/+11
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* synth: handle subprograms in package body.Tristan Gingold2019-10-081-0/+5
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* synth: infere_ff: handle pre-enable. Fix #964Tristan Gingold2019-10-081-23/+63
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* synth: handle case statement on bit vectors.Tristan Gingold2019-10-071-0/+23
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* synth: handle package bodies.Tristan Gingold2019-10-076-9/+69
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* synth-oper: handle to_bitvector, simplify.Tristan Gingold2019-10-071-9/+18
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* synth-disp_vhdl: handle enum of width 1 forTristan Gingold2019-10-071-2/+6
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* synth-oper: add support for more functions.Tristan Gingold2019-10-071-1/+51
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* synth: preliminary support for user packages.Tristan Gingold2019-10-074-84/+85
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* synth: allow unconnected port.Tristan Gingold2019-10-071-5/+7
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* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-071-3/+7
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* synth: propagate assignments out of subprograms. Fix #960Tristan Gingold2019-10-063-2/+43
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* netlists-dump: improve output for --out=rawTristan Gingold2019-10-061-4/+5
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* synth: revert patch on synth_subprogram_association.Tristan Gingold2019-10-063-8/+4
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* synth: handle subtypes in components. Fix #970Tristan Gingold2019-10-064-20/+61
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* ghdlsynth: fix crash when using libghdl.Tristan Gingold2019-10-061-2/+0
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* synth: fix crash for port subtype in component.Tristan Gingold2019-10-061-1/+1
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* synth: handle /= with non-matching length. For #968Tristan Gingold2019-10-061-6/+10
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* netlists: remove get_parent for instance.Tristan Gingold2019-10-061-2/+0
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* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-065-6/+5
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* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-0612-33/+34
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* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-064-9/+8
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* netlists: Remove Get_Name renaming for instances.Tristan Gingold2019-10-065-10/+9
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* synth: handle neg for integers.Tristan Gingold2019-10-061-0/+13
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* synth: add error messages for latches.Tristan Gingold2019-10-066-6/+198
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* netlists-dump: add prefix to numbers.Tristan Gingold2019-10-061-8/+8
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* synth: fix selected signal assignment (use basetype).Tristan Gingold2019-10-051-1/+1
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* synth: add support for comp. equal of two numeric signed (#966)T. Meissner2019-10-051-0/+4
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* synth: support block declarations.Tristan Gingold2019-10-051-2/+16
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* synth: minimal support for blocks. Fix #965Tristan Gingold2019-10-052-0/+19
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* netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.Tristan Gingold2019-10-041-0/+18
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* netlists-disp_vhdl: add qualification when needed for =Tristan Gingold2019-10-041-5/+24
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* netlists-disp_vhdl: handle empty operand for concat2, addTristan Gingold2019-10-041-1/+30
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* netlists-disp_vhdl: handle id_negTristan Gingold2019-10-041-0/+2
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* synth: preliminary work to support procedure calls.Tristan Gingold2019-10-041-118/+200
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* synth: factorize code to read memories.Tristan Gingold2019-10-043-74/+47
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* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-10-031-1/+1
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* synth-oper: convert type of unary operation operand.Tristan Gingold2019-10-033-4/+12
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* synth: factorize code for synth_target.Tristan Gingold2019-10-031-86/+24
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* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-035-13/+13
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* synth: remove unused wlen field of bound_type.Tristan Gingold2019-10-034-10/+1
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* synth-inference: minor improvement.Tristan Gingold2019-10-031-10/+9
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