iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Create_Instantiation_Bodies: add parent	Tristan Gingold	2016-09-30	1	-2/+3
*	vhdl08: more support for interface subprograms.	Tristan Gingold	2016-09-27	1	-1/+2
*	vhdl08: preliminary work for package body instantiation.	Tristan Gingold	2016-09-18	1	-0/+31
*	Handle macro-expansion of instantiation of declaration with interface type.	Tristan Gingold	2016-09-16	1	-19/+82
*	Comments and reformatting.	Tristan Gingold	2016-09-14	1	-114/+64
*	vhdl08: handle very simple nested packages.	Tristan Gingold	2016-09-03	1	-38/+8
*	vhdl08: preliminary work for nested package and type association.	Tristan Gingold	2016-09-01	1	-12/+20
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-19/+63
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-7/+40
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-17	1	-2/+0
*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-17	1	-0/+2
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-16/+42
*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-14	1	-1/+59
*	simul: add missing canon.	Tristan Gingold	2016-02-09	1	-3/+3
*	simul: handle vhdl 2008.	Tristan Gingold	2016-02-06	1	-45/+106
*	simul: fix various issues.	Tristan Gingold	2016-01-24	1	-1/+1
*	Add support for conditional assignments.	Tristan Gingold	2016-01-16	1	-16/+112
*	ghdl_simul debugger: handle function call, consider entity declarations.	Tristan Gingold	2015-11-30	1	-3/+0
*	canon: do not optimize concurrent procedure calls if not whole_analyze.	Tristan Gingold	2015-09-08	1	-2/+6
*	Add context declaration and reference (vhdl 2008).	Tristan Gingold	2015-05-12	1	-3/+5
*	Keep and handle simple name for Block_Specification.	Tristan Gingold	2015-01-16	1	-1/+1
*	canon: fix after previous change (do not generate default config for for-gen)	Tristan Gingold	2015-01-16	1	-1/+1
*	vhdl08: block configuration for if-generate statements.	Tristan Gingold	2015-01-10	1	-6/+17
*	Canon: do not free old concurrent statement.	Tristan Gingold	2015-01-08	1	-2/+0
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-2/+21
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-45/+72
*	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold	2014-12-15	1	-6/+1
*	iirs: reduce size of signal_declaration.	Tristan Gingold	2014-12-14	1	-1/+1
*	Put attribute_value_chain in parent.	Tristan Gingold	2014-12-14	1	-2/+0
*	Create src/vhdl subdirectory.	Tristan Gingold	2014-11-04	1	-0/+2735