iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl2008: allow out port in sensitivity lists.	Tristan Gingold	2017-03-27	1	-6/+20
*	Avoid a crash in case of invalid expression.	Tristan Gingold	2017-03-25	1	-1/+2
*	eval_is_in_bound: make it more tolerant.	Tristan Gingold	2017-01-19	1	-5/+10
*	vhdl08: allow PSL default clock declaration in block declarative parts.	Tristan Gingold	2017-01-13	1	-16/+12
*	ownership: check tree after sem and canon.	Tristan Gingold	2016-11-05	1	-1/+1
*	vhdl08: allow unaffected in sequential signal assignments.	Tristan Gingold	2016-11-01	1	-5/+8
*	Remove default_*_map_aspect from binding_indication.	Tristan Gingold	2016-10-20	1	-1/+1
*	Rework AST to setup ownership and reference policy.	Tristan Gingold	2016-10-11	1	-1/+1
*	vhdl08: create interface subprogram declaration.	Tristan Gingold	2016-09-19	1	-4/+5
*	sem_stmts: reformatting.	Tristan Gingold	2016-09-15	1	-4/+2
*	Avoid a crash on bad component name.	Tristan Gingold	2016-08-26	1	-5/+13
*	Rewrite most of error and warning messages.	Tristan Gingold	2016-08-02	1	-3/+3
*	Rewrite error messages.	Tristan Gingold	2016-08-02	1	-89/+89
*	Rewrite scan error messages: use formatting.	Tristan Gingold	2016-08-02	1	-7/+8
*	Rework warnings to have a uniq tag per warning.	Tristan Gingold	2016-08-01	1	-5/+6
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-32/+79
*	Fix indentation and English mistakes.	Tristan Gingold	2016-07-05	1	-10/+9
*	Avoid a crash on error.	Tristan Gingold	2016-03-26	1	-34/+33
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-1/+4
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-2/+3
*	Improve error message for variable assignment.	Tristan Gingold	2016-01-19	1	-1/+6
*	Add support for conditional assignments.	Tristan Gingold	2016-01-16	1	-312/+307
*	Suppress stack switching; save process state in secondary stack.	Tristan Gingold	2015-09-04	1	-1/+6
*	Adjust previous patch: set parent.	Tristan Gingold	2015-07-15	1	-0/+2
*	Convert psl assertion to normal assertion if simple expression.	Tristan Gingold	2015-07-10	1	-21/+22
*	Improve code generation of strings.	Tristan Gingold	2015-06-27	1	-0/+1
*	Add suspend_flag.	Tristan Gingold	2015-06-07	1	-1/+47
*	Handle signal attribute in declarations. Fix alias of implicit signal.	Tristan Gingold	2015-05-27	1	-40/+0
*	Style fix.	Tristan Gingold	2015-01-23	1	-5/+2
*	vhdl2008: expanded names in for-generate statements.	Tristan Gingold	2015-01-12	1	-0/+2
*	vhdl2008: handle expanded names in if-generate statements.	Tristan Gingold	2015-01-12	1	-0/+5
*	vhdl08: block configuration for if-generate statements.	Tristan Gingold	2015-01-10	1	-6/+19
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-14/+27
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-36/+69
*	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold	2014-12-15	1	-6/+6
*	iirs: reduce size of signal_declaration.	Tristan Gingold	2014-12-14	1	-1/+1
*	sem_stmt: avoid crash after error on concurrent procedure call in entity.	Tristan Gingold	2014-11-28	1	-1/+3
*	Create src/vhdl subdirectory.	Tristan Gingold	2014-11-04	1	-0/+2007