iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-192/+0
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*	simulation: refactoring (move block_instance to iir_values).	Tristan Gingold	2017-11-24	1	-2/+1
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*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	1	-0/+7
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*	simul: fix local protected object, boolean for-generate loop	Tristan Gingold	2016-02-14	1	-0/+1
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*	simul: preliminary work to support PSL.	Tristan Gingold	2016-02-14	1	-0/+7
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*	simul: handle vhdl 2008.	Tristan Gingold	2016-02-06	1	-3/+5
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*	simul: handle default assignment to unconstrained ports.	Tristan Gingold	2016-01-24	1	-9/+0
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*	Move translate and simulate.	Tristan Gingold	2014-11-05	1	-0/+185