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vhdl
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simulate
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simul-annotations.adb
Commit message (
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Author
Age
Files
Lines
*
simul: Add ref in info to ease debugging.
Tristan Gingold
2017-12-21
1
-0
/
+23
*
simul: add Kind_Protected instead of reusing Kind_Frame.
Tristan Gingold
2017-12-21
1
-1
/
+7
*
simul: handle psl endpoints (and adjust issue45).
Tristan Gingold
2017-12-21
1
-0
/
+2
*
simul: handle selected signal assignments.
Tristan Gingold
2017-12-21
1
-0
/
+1
*
simul: create initial driver value.
Tristan Gingold
2017-12-21
1
-2
/
+2
*
simul: fix crash while calling foreign subprogram.
Tristan Gingold
2017-12-11
1
-2
/
+2
*
simul: fix annotation of macro-expanded package instantiation.
Tristan Gingold
2017-12-07
1
-5
/
+16
*
simul: handle interface type.
Tristan Gingold
2017-12-07
1
-1
/
+2
*
simul: handle nested package instantiation.
Tristan Gingold
2017-12-07
1
-1
/
+3
*
simul: fix choice list for case generate statement.
Tristan Gingold
2017-12-05
1
-2
/
+4
*
simul: psl default clock, unaffected waveform.
Tristan Gingold
2017-12-05
1
-0
/
+3
*
simul: handle interface subprogram.
Tristan Gingold
2017-12-05
1
-1
/
+4
*
simul: handle package interface, remove iir_value_environment.
Tristan Gingold
2017-12-05
1
-8
/
+8
*
simul: handle instantiated package.
Tristan Gingold
2017-12-05
1
-4
/
+11
*
simul: add support for case generate statetement.
Tristan Gingold
2017-12-04
1
-0
/
+15
*
simul: support nested packages.
Tristan Gingold
2017-12-04
1
-54
/
+59
*
simul: Remove scope_type (unused).
Tristan Gingold
2017-12-03
1
-152
/
+14
*
simul: add global_info.
Tristan Gingold
2017-12-03
1
-32
/
+45
*
simul: refactoring: scope is now the corresponding sim_info.
Tristan Gingold
2017-12-03
1
-22
/
+18
*
Create the simul.ads package (for a namespace).
Tristan Gingold
2017-11-24
1
-0
/
+1345