index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
vhdl
/
translate
/
trans-chap1.adb
Commit message (
Expand
)
Author
Age
Files
Lines
*
vhdl/translate: elaborate dependencies of configurations. Fix #984
Tristan Gingold
2019-10-24
1
-0
/
+4
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-1
/
+2
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
1
-1
/
+1
*
Use flist for disconnection specification and component specification.
Tristan Gingold
2017-11-08
1
-3
/
+2
*
Use Flist for array indexes.
Tristan Gingold
2017-11-06
1
-2
/
+2
*
Translation: separate subprogram translation spec and body.
Tristan Gingold
2017-05-18
1
-1
/
+2
*
Create default value for ports.
Tristan Gingold
2017-05-09
1
-0
/
+12
*
translate: refactoring for ortho_info_type.
Tristan Gingold
2016-12-30
1
-7
/
+7
*
canon: do not set formal of association by position.
Tristan Gingold
2016-10-19
1
-1
/
+13
*
Rewrite error messages.
Tristan Gingold
2016-08-02
1
-1
/
+1
*
vhdl08: add support of case-generate statement
Tristan Gingold
2016-07-07
1
-40
/
+42
*
Initial support of direct recursive instantiation.
Tristan Gingold
2016-07-03
1
-13
/
+46
*
translation: avoid memory leak while allocating ports.
Tristan Gingold
2016-03-16
1
-1
/
+1
*
translate: separate decl and stmt elab subprograms.
Tristan Gingold
2016-02-23
1
-52
/
+77
*
grt: remove rti field in signals (to reduce space).
Tristan Gingold
2016-02-21
1
-1
/
+0
*
ortho: rename start/finish_const_value to start/finish_init_value.
Tristan Gingold
2016-02-21
1
-2
/
+2
*
Pass signal values to interfaces. 'sigptr' optimization.
Tristan Gingold
2015-12-18
1
-1
/
+6
*
Allow generic without default values in top-level entity.
Tristan Gingold
2015-05-11
1
-2
/
+17
*
Elaborate generics in two steps. Fix -c/-e for llvm builds.
Tristan Gingold
2015-03-01
1
-25
/
+12
*
Keep and handle simple name for Block_Specification.
Tristan Gingold
2015-01-16
1
-1
/
+1
*
vhdl08: block configuration for if-generate statements.
Tristan Gingold
2015-01-10
1
-2
/
+4
*
Handle vhdl08 if generate statements
Tristan Gingold
2015-01-07
1
-16
/
+24
*
Initial rework for vhdl 2008 generate statements.
Tristan Gingold
2015-01-03
1
-142
/
+170
*
Translate_Range: use mnodes.
Tristan Gingold
2014-11-16
1
-5
/
+4
*
Split translation into child packages.
Tristan Gingold
2014-11-09
1
-0
/
+843