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trans-rtis.adb
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Author
Age
Files
Lines
*
ignore restrict in simulation (#897)
Pepijn de Vos
2019-08-20
1
-3
/
+3
*
Add support for PSL assumptions, used in formal verification (#880)
Pepijn de Vos
2019-08-07
1
-4
/
+12
*
vhdl: rename Cover_Statement to Cover_Directive.
Tristan Gingold
2019-07-04
1
-4
/
+4
*
vhdl: add anonymous_signal_declaration.
Tristan Gingold
2019-07-03
1
-3
/
+6
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-1
/
+1
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
1
-1
/
+1
*
vhdl: move configuration package as a vhdl child.
Tristan Gingold
2019-05-05
1
-2
/
+2
*
trans-rtis: take into account instances in the count of packages.
Tristan Gingold
2018-11-24
1
-4
/
+15
*
trans-rtis: fix uninitialized variable.
Tristan Gingold
2018-10-24
1
-3
/
+8
*
Rework translation of unbounded and complex types.
Tristan Gingold
2018-10-21
1
-122
/
+127
*
translate: remove other use of Nam_Buffer.
Tristan Gingold
2018-01-20
1
-13
/
+7
*
Rework array/record type mode to improve support of constrained records.
Tristan Gingold
2018-01-11
1
-15
/
+19
*
Use flist for enumerations.
Tristan Gingold
2017-11-07
1
-2
/
+2
*
Use Flist for records.
Tristan Gingold
2017-11-07
1
-3
/
+2
*
Use Flist for array indexes.
Tristan Gingold
2017-11-06
1
-2
/
+2
*
unbounded records: add rti support (WIP)
Tristan Gingold
2017-02-21
1
-55
/
+76
*
vhdl08: allow PSL default clock declaration in block declarative parts.
Tristan Gingold
2017-01-13
1
-0
/
+5
*
WIP for unconstrained records.
Tristan Gingold
2017-01-13
1
-1
/
+1
*
translate: WIP - refactoring for unbounded records.
Tristan Gingold
2017-01-02
1
-1
/
+1
*
translate: WIP for unbounded records.
Tristan Gingold
2017-01-02
1
-1
/
+1
*
translate: refactoring for ortho_info_type.
Tristan Gingold
2016-12-30
1
-19
/
+19
*
vhdl08: support top-level macro-expanded package instantiation declarations.
Tristan Gingold
2016-12-05
1
-4
/
+7
*
WIP for nested instantiation of macro-expansed packages.
Tristan Gingold
2016-11-12
1
-17
/
+23
*
Add signal_attribute_declaration to hold implicit atribute signals.
Tristan Gingold
2016-10-08
1
-20
/
+29
*
Rework range_expression and incomplete type for instantiation.
Tristan Gingold
2016-09-30
1
-3
/
+2
*
vhdl08: strengthten nested packages.
Tristan Gingold
2016-09-12
1
-1
/
+8
*
vhdl08: preliminary work to support nested package bodies.
Tristan Gingold
2016-09-04
1
-0
/
+11
*
vhdl08: handle very simple nested packages.
Tristan Gingold
2016-09-03
1
-58
/
+76
*
vhdl08: add support of case-generate statement
Tristan Gingold
2016-07-07
1
-16
/
+49
*
PSL: add clocked SERE, make endpoints visible from VHDL.
Tristan Gingold
2016-03-22
1
-3
/
+11
*
PSL: add counters, generate rti and add --psl-report
Tristan Gingold
2016-03-18
1
-30
/
+51
*
ortho: rename start/finish_const_value to start/finish_init_value.
Tristan Gingold
2016-02-21
1
-44
/
+44
*
Pass signal values to interfaces. 'sigptr' optimization.
Tristan Gingold
2015-12-18
1
-1
/
+1
*
trans-rtis: fix uninitialized field (that could result in a crash).
Tristan Gingold
2015-09-15
1
-10
/
+8
*
Replace fat accesses by bounds accesses
Tristan Gingold
2015-08-29
1
-19
/
+23
*
Handle vhdl08 if generate statements
Tristan Gingold
2015-01-07
1
-186
/
+302
*
Rework for vhdl08 generate: change rtis.
Tristan Gingold
2015-01-04
1
-82
/
+193
*
Initial rework for vhdl 2008 generate statements.
Tristan Gingold
2015-01-03
1
-37
/
+75
*
Rename name_table.name_buffer and name_length to avoid clash.
Tristan Gingold
2014-12-31
1
-6
/
+6
*
Use same node for implicit and explicit subprogram declarations.
Tristan Gingold
2014-12-15
1
-6
/
+2
*
iirs: reduce size of signal_declaration.
Tristan Gingold
2014-12-14
1
-3
/
+9
*
rtis: add source location for blocks and object. Use them in fst dumper.
Tristan Gingold
2014-12-13
1
-27
/
+97
*
Split translation into child packages.
Tristan Gingold
2014-11-09
1
-0
/
+2559