| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rework list implementation, use iterator. | Tristan Gingold | 2017-11-11 | 1 | -8/+10 |
| * | Create default value for ports. | Tristan Gingold | 2017-05-09 | 1 | -2/+1 |
| * | vhdl08: allow unaffected in sequential signal assignments. | Tristan Gingold | 2016-11-01 | 1 | -15/+52 |
| * | Add translation for selected signal assignment. | Tristan Gingold | 2016-11-01 | 1 | -2/+26 |
| * | canon: do not set formal of association by position. | Tristan Gingold | 2016-10-19 | 1 | -8/+2 |
| * | Rewrite most of error and warning messages. | Tristan Gingold | 2016-08-02 | 1 | -2/+4 |
| * | Add support for conditional assignments. | Tristan Gingold | 2016-01-16 | 1 | -12/+27 |
| * | Move translate and simulate. | Tristan Gingold | 2014-11-05 | 1 | -0/+182 |
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index : iCE40/ghdl | |
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