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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-1/+1
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+2
* synth: handle verification units.Tristan Gingold2019-08-201-31/+57
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-0/+2
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-27/+37
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+2
* vhdl: cleanup in clear_instantiation_configuration.Tristan Gingold2019-07-131-2/+2
* vhdl: minor reformating.Tristan Gingold2019-07-111-3/+3
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-14/+26
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-13/+61
* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-2/+2
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* Extract psl-errors from errorout.Tristan Gingold2019-05-101-1/+2
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
* vhdl: remove too strict assertion in canon. Fix #816Tristan Gingold2019-05-071-11/+3
* vhdl-nodes_utils: renaming.Tristan Gingold2019-05-071-13/+13
* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-061-11/+12
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* vhdl: move sem* packages to vhdl children.Tristan Gingold2019-05-051-3/+3
* vhdl: move canon to a vhdl child package.Tristan Gingold2019-05-051-0/+3290