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* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-0/+2
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-0/+2
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-2/+2
* vhdl-errors.adb: use normal message subprogram. For #2070Tristan Gingold2022-06-011-9/+1
* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-0/+6
* vhdl-errors(disp_node): change message for generate bodyTristan Gingold2022-05-141-1/+1
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-0/+2
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-3/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-0/+1
* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+3
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+4
* update license headersumarcor2021-01-141-11/+9
* vhdl: improve error message for invalid record element constraint.Tristan Gingold2020-12-311-1/+1
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+4
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+4
* vhdl: --std93c is now an alias for --std=93 -frelaxedTristan Gingold2020-06-131-1/+1
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+8
* synth: correctly quote nets name in error messages.Tristan Gingold2020-05-091-1/+1
* vhdl: fix handling of types name in name attributes. Fix #1268Tristan Gingold2020-04-271-0/+1
* vhdl-errors: give an hint for -frelaxed. Fix #1152Tristan Gingold2020-03-061-0/+10
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-1/+2
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+6
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+4
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-4/+62
* Rework errors handling, to have a more generic framework.Tristan Gingold2019-10-061-0/+56
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-0/+2
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+6
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+3
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+2
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+3
* vhdl: improve error messages for generate statement.Tristan Gingold2019-06-121-1/+1
* vhdl-errors: avoid a crash on error type.Tristan Gingold2019-06-051-0/+3
* errorout: add messages group instead of continuation.Tristan Gingold2019-05-121-15/+10
* vhdl: minor reformating.Tristan Gingold2019-05-111-4/+3
* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-8/+13
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-3/+3
* Extract psl-errors from errorout.Tristan Gingold2019-05-101-5/+0
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+990