| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | synthesis: add option --vendor-library= for synthesis. | Tristan Gingold | 2020-03-10 | 1 | -0/+16 |
| * | ams-vhdl: add support for 'delayed for quantity. | Tristan Gingold | 2019-12-31 | 1 | -0/+1 |
| * | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 1 | -1/+36 |
| * | ams-vhdl: add simultaneous null statement. | Tristan Gingold | 2019-12-30 | 1 | -0/+2 |
| * | ams-vhdl: check nature for record natures and terminals. | Tristan Gingold | 2019-12-30 | 1 | -0/+16 |
| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 1 | -13/+391 |
| * | vhdl: add Has_Delay_Machanism for optional 'inertial' printing. | Tristan Gingold | 2019-12-26 | 1 | -0/+16 |
| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 1 | -0/+32 |
| * | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 1 | -9/+9 |
| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -1/+17 |
| * | vhdl: parse verification unit (WIP). | Tristan Gingold | 2019-08-17 | 1 | -2/+3 |
| * | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -3/+54 |
| * | vhdl: remove unused Get/Set_Choice_Order. | Tristan Gingold | 2019-08-09 | 1 | -16/+0 |
| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 |
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 |
| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -0/+1 |
| * | vhdl: add anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+1 |
| * | vhdl-disp_vhdl: print literals and identifiers from the source. | Tristan Gingold | 2019-05-29 | 1 | -0/+16 |
| * | vhdl: get rid of Get/Set_Physical_Unit. | Tristan Gingold | 2019-05-28 | 1 | -18/+2 |
| * | vhdl: add hook on free_node, automatically free | Tristan Gingold | 2019-05-22 | 1 | -10/+33 |
| * | vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64. | Tristan Gingold | 2019-05-10 | 1 | -26/+26 |
| * | Make lists a generic package, add vhdl-lists. | Tristan Gingold | 2019-05-09 | 1 | -1/+1 |
| * | vhdl: move nodes_meta package to vhdl child. | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -0/+6569 |
