iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-0/+2
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-1/+6
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-0/+13
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-0/+6
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-1/+7
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-0/+1
*	vhdl: recognize to_bitvector.	Tristan Gingold	2019-10-07	1	-0/+2
*	vhdl: recognize div operators.	Tristan Gingold	2019-09-30	1	-0/+7
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	1	-0/+5
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	1	-0/+22
*	vhdl-nodes: add a comment.	Tristan Gingold	2019-09-12	1	-1/+1
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	1	-0/+5
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	1	-0/+7
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-3/+4
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	1	-0/+4
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	1	-0/+7
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	1	-0/+2
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	1	-0/+4
*	synth: handle verification units.	Tristan Gingold	2019-08-20	1	-1/+13
*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-23/+30
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-6/+58
*	add synthesis support for logic operators on numeric types (#893)	Pepijn de Vos	2019-08-15	1	-0/+21
*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	1	-0/+4
*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	1	-7/+0
*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	1	-15/+16
*	vhdl-nodes: gather PSL nodes, regenerate nodes_meta.	Tristan Gingold	2019-08-07	1	-30/+4
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-5/+12
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-0/+2
*	vhdl: linearize analyze and evaluation of concat operators.	Tristan Gingold	2019-07-26	1	-0/+1
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	1	-1/+5
*	vhdl: recognize resize function.	Tristan Gingold	2019-07-24	1	-0/+5
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	1	-0/+8
*	vhdl-nodes: add comments	Tristan Gingold	2019-07-11	1	-0/+16
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-5/+5
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-1/+32
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-0/+26
*	vhdl: recognize more predefined std_logic_unsigned functions.	Tristan Gingold	2019-06-30	1	-0/+8
*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	1	-0/+6
*	vhdl: recognize std_logic_unsigned	Tristan Gingold	2019-06-29	1	-1/+6
*	vhdl: recognize some functions of math_real.	Tristan Gingold	2019-06-28	1	-1/+5
*	vhdl: recognize more numeric_std predefined functions.	Tristan Gingold	2019-06-23	1	-0/+35
*	vhdl: recognize to_integer/to_signed/to_unsigned.	Tristan Gingold	2019-06-20	1	-0/+7
*	vhdl-nodes: add Node_List and Node_Flist aliases.	Tristan Gingold	2019-06-12	1	-0/+2
*	synth: added support for numeric_std unary negation	Christos Gentsos	2019-06-06	1	-1/+5
*	synth: handle numeric_std subtraction (addition was already there)	Christos Gentsos	2019-06-06	1	-0/+7
*	vhdl: renames disp_vhdl to prints	Tristan Gingold	2019-05-30	1	-1/+3
*	vhdl-disp_vhdl: print literals and identifiers from the source.	Tristan Gingold	2019-05-29	1	-16/+30
*	vhdl: get rid of Get/Set_Physical_Unit.	Tristan Gingold	2019-05-28	1	-10/+3
*	vhdl: update AMS parsing.	Tristan Gingold	2019-05-24	1	-0/+4
*	vhdl-parse: Add Has_Is for block_statement.	Tristan Gingold	2019-05-24	1	-0/+2