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* vhdl: recognize resize function.Tristan Gingold2019-07-241-0/+5
* synth: add > and >= operators (#870)Pepijn de Vos2019-07-161-0/+8
* vhdl-nodes: add commentsTristan Gingold2019-07-111-0/+16
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-5/+5
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-1/+32
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+26
* vhdl: recognize more predefined std_logic_unsigned functions.Tristan Gingold2019-06-301-0/+8
* synth: handle std_logic_unsigned."+"Tristan Gingold2019-06-301-0/+6
* vhdl: recognize std_logic_unsignedTristan Gingold2019-06-291-1/+6
* vhdl: recognize some functions of math_real.Tristan Gingold2019-06-281-1/+5
* vhdl: recognize more numeric_std predefined functions.Tristan Gingold2019-06-231-0/+35
* vhdl: recognize to_integer/to_signed/to_unsigned.Tristan Gingold2019-06-201-0/+7
* vhdl-nodes: add Node_List and Node_Flist aliases.Tristan Gingold2019-06-121-0/+2
* synth: added support for numeric_std unary negationChristos Gentsos2019-06-061-1/+5
* synth: handle numeric_std subtraction (addition was already there)Christos Gentsos2019-06-061-0/+7
* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-1/+3
* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-16/+30
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-10/+3
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-0/+4
* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-0/+2
* vhdl-nodes: make subtype_Definition like the others.Tristan Gingold2019-05-231-0/+4
* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-0/+4
* vhdl-nodes: fix minor typo.Tristan Gingold2019-05-111-1/+1
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-4/+10
* Make lists a generic package, add vhdl-lists.Tristan Gingold2019-05-091-1/+1
* flists is now a generic package, add vhdl-flistsTristan Gingold2019-05-091-1/+1
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-0/+7549