iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: handle reduction operators. Fix #1342	Tristan Gingold	2020-05-27	1	-2/+6
*	vhdl-nodes: use a flag field for direction.	Tristan Gingold	2020-05-20	1	-2/+2
*	vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325	Tristan Gingold	2020-05-19	1	-9/+9
*	synth: handle functional call to numeric_std binary operators. For #1313	Tristan Gingold	2020-05-16	1	-24/+33
*	vhdl: allow attribute specifications in protected types. For #1252	Tristan Gingold	2020-04-20	1	-44/+48
*	types: introduce Direction_Type, which replaces Iir_Direction.	Tristan Gingold	2020-04-20	1	-8/+2
*	vhdl: handling attribute specification in instantiations. Fix #1229	Tristan Gingold	2020-04-16	1	-3/+3
*	synth-oper: recognize more operations from std_logic_arith.	Tristan Gingold	2020-04-12	1	-0/+26
*	vhdl: recognize math_real.floor. For #1210	Tristan Gingold	2020-04-11	1	-0/+1
*	vhdl: recognize ext/sxt from std_logic_arith.	Tristan Gingold	2020-04-11	1	-0/+3
*	vhdl: recognize comparaison of std_logic_arith.	Tristan Gingold	2020-04-11	1	-0/+54
*	vhdl: add scalar_size. Size of scalar types is computed during analysis.	Tristan Gingold	2020-04-06	1	-1/+24
*	vhdl: recognize reduce functions in std_logic_misc.	Tristan Gingold	2020-03-28	1	-1/+15
*	vhdl: move get_subprogram_body_origin to vhdl-sem_inst.	Tristan Gingold	2020-03-24	1	-0/+11
*	synth: handle ieee.numeric_std.to_01	Tristan Gingold	2020-03-22	1	-0/+3
*	vhdl: recognize minimum/maximum in numeric_std. For #1168	Tristan Gingold	2020-03-21	1	-0/+14
*	synth: handle more operations from synsopsys packages.	Tristan Gingold	2020-03-14	1	-8/+12
*	vhdl: recognize more std_logic_arith operations.	Tristan Gingold	2020-03-13	1	-1/+37
*	vhdl-ieee-std_logic_arith: recognize more conversions.	Tristan Gingold	2020-03-11	1	-1/+6
*	vhdl: recognize mod/rem operators.	Tristan Gingold	2020-03-10	1	-0/+14
*	synthesis: add option --vendor-library= for synthesis.	Tristan Gingold	2020-03-10	1	-0/+9
*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	1	-0/+6
*	synth: handle some rotation and shifts. Fix #1077	Tristan Gingold	2020-01-30	1	-0/+5
*	synth: handle matching comparisons. Fix #1109	Tristan Gingold	2020-01-24	1	-0/+42
*	synth: add id_abs gate. For #1101	Tristan Gingold	2020-01-20	1	-0/+2
*	synth: handle more signed operations. For #1101	Tristan Gingold	2020-01-19	1	-0/+4
*	vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077	Tristan Gingold	2020-01-11	1	-0/+9
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	1	-0/+1
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	1	-0/+4
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-0/+25
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	1	-0/+39
*	ams-vhdl: add frequency function, minor fixes.	Tristan Gingold	2019-12-30	1	-0/+1
*	ams-vhdl: improve error recovery	Tristan Gingold	2019-12-30	1	-0/+1
*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	1	-2/+7
*	ams-vhdl: fix tree consistency for terminal declaration.	Tristan Gingold	2019-12-30	1	-2/+2
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	1	-1/+15
*	vhdl-ams: fix tree consistency for subnature declaration.	Tristan Gingold	2019-12-29	1	-4/+4
*	vhdl-ams: fix overload for simple simultaneous statement.	Tristan Gingold	2019-12-29	1	-0/+4
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	1	-28/+643
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	1	-0/+11
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	1	-0/+3
*	vhdl: recognize sin and cos from math_real.	Tristan Gingold	2019-11-26	1	-0/+2
*	synth: preliminary work to support intrinsic procedures.	Tristan Gingold	2019-11-14	1	-0/+5
*	vhdl: recognize rising_edge/falling_edge.	Tristan Gingold	2019-11-06	1	-0/+3
*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	1	-0/+2
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-0/+2
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-1/+6
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-0/+13
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-0/+6
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-1/+7