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* vhdl: allow attribute specifications in protected types. For #1252Tristan Gingold2020-04-201-252/+256
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-25/+25
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-240/+286
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-210/+225
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+45
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-29/+119
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-87/+123
* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-1/+2
* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-86/+92
* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-301-1/+1
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-225/+247
* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-1/+1
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-379/+1315
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-91/+121
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-197/+203
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-63/+107
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-11/+11
* synth: handle verification units.Tristan Gingold2019-08-201-202/+226
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-243/+256
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-263/+392
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-152/+156
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-275/+247
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-84/+86
* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-071-95/+87
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-101/+137
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-261-1/+13
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-18/+18
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-89/+121
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-151/+173
* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-264/+292
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-280/+258
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-172/+176
* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-1/+3
* vhdl-nodes: make subtype_Definition like the others.Tristan Gingold2019-05-231-201/+205
* vhdl-nodes: fix minor typo.Tristan Gingold2019-05-111-54/+50
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-50/+50
* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-061-0/+10786
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