| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 1 | -0/+4 |
| * | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 1 | -2/+2 |
| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -0/+2 |
| * | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -0/+6 |
| * | vhdl: remove unused Get/Set_Choice_Order. | Tristan Gingold | 2019-08-09 | 1 | -2/+0 |
| * | vhdl-disp_vhdl: print literals and identifiers from the source. | Tristan Gingold | 2019-05-29 | 1 | -0/+2 |
| * | vhdl: get rid of Get/Set_Physical_Unit. | Tristan Gingold | 2019-05-28 | 1 | -2/+0 |
| * | psl: add psl-types, psl-nodes_priv. | Tristan Gingold | 2019-05-10 | 1 | -0/+1 |
| * | vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64. | Tristan Gingold | 2019-05-10 | 1 | -12/+12 |
| * | vhdl: move nodes_meta package to vhdl child. | Tristan Gingold | 2019-05-06 | 1 | -0/+924 |
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index : iCE40/ghdl | |
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