iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: parse and analyze force/release signal assignment statements.	Tristan Gingold	2020-08-01	1	-0/+31
*	Synthesis of PSL built-in fell() function.	tmeissner	2020-06-07	1	-0/+17
*	Synthesis of PSL built-in rose() function.	tmeissner	2020-06-06	1	-0/+17
*	Synthesis of PSL stable() function.	tmeissner	2020-06-06	1	-0/+17
*	vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662	Tristan Gingold	2020-06-02	1	-1/+25
*	types: introduce Direction_Type, which replaces Iir_Direction.	Tristan Gingold	2020-04-20	1	-1/+1
*	vhdl-prints: handle evaluated expression for qualified_expression.	Tristan Gingold	2020-04-18	1	-16/+19
*	psl: keep denoting names in the PSL ast.	Tristan Gingold	2020-03-13	1	-1/+2
*	vhdl-prints: disable code to display anonymous signal.	Tristan Gingold	2020-03-02	1	-2/+10
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	1	-0/+2
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-8/+7
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	1	-40/+89
*	ams-vhdl: handle record nature end name.	Tristan Gingold	2019-12-30	1	-0/+2
*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	1	-1/+36
*	ams-vhdl: print subnature declarations.	Tristan Gingold	2019-12-30	1	-1/+16
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	1	-127/+405
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	1	-0/+2
*	vhdl-prints: subtype indication is optional in object alias.	Tristan Gingold	2019-12-26	1	-3/+2
*	vhdl-prints: handle more constructs in psl vunit.	Tristan Gingold	2019-10-31	1	-0/+5
*	vhdl-prints: do not crash on vunit declarations.	Tristan Gingold	2019-10-23	1	-0/+4
*	psl: add active state.	Tristan Gingold	2019-10-21	1	-0/+7
*	vhdl-prints: handle restrict in vunit.	Tristan Gingold	2019-10-21	1	-0/+2
*	vhdl-prints: add parenthesis around boolean and/or.	Tristan Gingold	2019-10-18	1	-0/+4
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-3/+4
*	vhdl psl: fully scan PSL keywords in scanner.	Tristan Gingold	2019-08-20	1	-1/+1
*	vhdl-prints: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	1	-0/+7
*	vhdl-prints: handle verification units.	Tristan Gingold	2019-08-20	1	-318/+354
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-0/+13
*	vhdl: add PSL keywords to vhdl08 reserved words.	Tristan Gingold	2019-08-14	1	-6/+6
*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	1	-1/+5
*	vhdl: handle subtype indication (with range) in discrete_range.	Tristan Gingold	2019-08-10	1	-0/+2
*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	1	-5/+4
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-4/+24
*	vhdl-prints: improve output for ports/generics.	Tristan Gingold	2019-07-22	1	-5/+27
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-6/+6
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-1/+18
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-0/+13
*	vhdl-prints: try to print error content.	Tristan Gingold	2019-06-04	1	-0/+10
*	vhdl-prints: fix extra 'else' in disp_conditional_waveform.	Tristan Gingold	2019-06-03	1	-2/+3
*	vhdl-prints: improve indent.	Tristan Gingold	2019-06-02	1	-0/+4
*	vhdl-prints: improve output for if/then, architecture.	Tristan Gingold	2019-06-01	1	-0/+4
*	vhdl-formatters: add indent.	Tristan Gingold	2019-06-01	1	-1/+5
*	vhdl-prints: handle PSL, add psl tokens for strong and inclusive variants.	Tristan Gingold	2019-05-30	1	-85/+394
*	vhdl: renames disp_vhdl to prints	Tristan Gingold	2019-05-30	1	-0/+4155