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* vhdl: handle selected waveform assignmentTristan Gingold2023-03-091-42/+47
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* vhdl-sem_stmts: simplify code, add commentsTristan Gingold2022-12-231-27/+5
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* trans-chap5.adb: handle package association in entities.Tristan Gingold2022-12-231-1/+1
| | | | Fix #2264
* vhdl-sem_inst: add instantiate_component_declaration.Tristan Gingold2022-12-231-1/+80
| | | | For #2264
* vhdl: minor refactoringTristan Gingold2022-12-121-3/+5
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* vhdl: fix use clause of a package with interface subprograms.Tristan Gingold2022-11-301-2/+2
| | | | Fix #2250
* vhdl-sem_stmts: handle external signal names in force assign. Fix #2173Tristan Gingold2022-08-111-1/+5
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* vhdl-sem_stmts.adb: handle signal assignment to external names. Fix #2172Tristan Gingold2022-08-111-0/+4
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* vhdl-sem_stmts: set stop_flag on call to stop and severity failure.Tristan Gingold2022-07-291-22/+56
| | | | Fix #2150
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-1/+1
| | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
* vhdl: warns on unused component declarationsTristan Gingold2021-09-301-0/+3
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* vhdl: move check on instantiation name from sem to parse.Tristan Gingold2021-07-281-1/+1
| | | | Fix #1823
* vhdl-sem_stmts.adb: avoid a crash when forced analysis.Tristan Gingold2021-07-231-0/+4
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* vhdl-sem_stmts.adb: avoid a crash on invalid expressionTristan Gingold2021-07-051-1/+3
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* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-0/+1
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* vhdl: avoid a crash on forced analysis of a erroneous name expressionTristan Gingold2021-05-281-2/+6
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* vhdl-sem_stmts.adb: avoid duplicate error messageTristan Gingold2021-05-281-0/+3
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* vhdl-sem_stmts: handle aliases for force/release assignment. Fix #1751Tristan Gingold2021-05-061-5/+8
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* Add a warning for processes without a wait statement. Fix #1677Tristan Gingold2021-03-081-7/+13
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* vhdl-sem_stmts: avoid overflow. Fix #1639Tristan Gingold2021-02-101-3/+13
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* update license headersumarcor2021-01-141-11/+9
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* vhdl-sem_stmts: fix typo (#1518)Douwe den Blanken2020-11-201-1/+1
| | | | | "time must be **greather** than previous transaction" -> "time must be **greater** than previous transaction" (h was in the word 'greater')
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-16/+165
| | | | For #1416
* vhdl: improve support of subtype attribute.Tristan Gingold2020-07-181-14/+35
| | | | | A subtype definition does not mean anymore that the subtype is constrained. It is now defined by the subtype indication of the name.
* vhdl: --std93c is now an alias for --std=93 -frelaxedTristan Gingold2020-06-131-4/+2
| | | | This simplifies the definition of --std=93c
* vhdl-parse: always keep parentheses in case expression. For #1364Tristan Gingold2020-06-131-0/+4
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* vhdl-sem_stmts: improve error message for signal assignment.Tristan Gingold2020-03-061-0/+9
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* vhdl: relax rule for choice expression staticness.Tristan Gingold2020-01-151-0/+9
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+34
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-1/+1
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* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-0/+7
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-0/+27
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* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-291-3/+17
| | | | Fix tree consistency for branch quantity declarations.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-43/+238
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* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-251-93/+88
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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+8
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-4/+5
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-1/+1
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-2/+9
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: add a comment.Tristan Gingold2019-07-161-0/+3
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-2/+2
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+2
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* vhdl: improve error messages for generate statement.Tristan Gingold2019-06-121-1/+1
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* vhdl: detect unused signals and variables.Tristan Gingold2019-06-051-1/+2
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* vhdl-sem_stmts.adb: minor refactoring.Tristan Gingold2019-05-281-1/+1
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* errorout: add messages group instead of continuation.Tristan Gingold2019-05-121-4/+6
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-1/+1
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
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