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* PSL: add clocked SERE, make endpoints visible from VHDL.Tristan Gingold2016-03-2217-237/+423
* Create psl_endpoint_declaration.Tristan Gingold2016-03-204-169/+226
* wip.Tristan Gingold2016-03-201-1/+3
* PSL: add counters, generate rti and add --psl-reportTristan Gingold2016-03-184-57/+66
* PSL translate: handle bit type.Tristan Gingold2016-03-181-4/+8
* translation: avoid memory leak while allocating ports.Tristan Gingold2016-03-164-18/+36
* trans-chap12: extract gen_stubs from write_list_list.Tristan Gingold2016-03-112-13/+54
* simulation: reuse Mode_Signal_Type from grt.types.Tristan Gingold2016-03-105-72/+76
* elaboration: use std_time to represent time in signal table.Tristan Gingold2016-03-103-9/+9
* simulation: add block id.Tristan Gingold2016-03-103-1/+13
* simul debugger: display packages and configuration.Tristan Gingold2016-03-101-2/+12
* trans-chap12: refactor.Tristan Gingold2016-03-072-53/+70
* translate: separate decl and stmt elab subprograms.Tristan Gingold2016-02-236-96/+319
* translate: minor reformating.Tristan Gingold2016-02-211-24/+19
* grt: remove rti field in signals (to reduce space).Tristan Gingold2016-02-211-1/+0
* ortho: rename start/finish_const_value to start/finish_init_value.Tristan Gingold2016-02-218-64/+64
* trans-chap12: factorize code.Tristan Gingold2016-02-201-9/+1
* Refactoring in simulate in order to link with ortho.Tristan Gingold2016-02-2016-1213/+1307
* parse: detect early use of signature in expressions.Tristan Gingold2016-02-181-1/+8
* parse: avoid weird error message for end protected.Tristan Gingold2016-02-171-1/+8
* assocations: check rules for unconstrained formal (LRM08 5.3.2.2 e 3)Tristan Gingold2016-02-172-4/+39
* Tentative fix for issue43.Tristan Gingold2016-02-171-1/+1
* Fix crash of issue42.Tristan Gingold2016-02-171-1/+2
* simul debugger: add info instancesTristan Gingold2016-02-172-3/+46
* psl: cover directive works on a sequence, not on a property.Tristan Gingold2016-02-171-2/+0
* PSL: move canon code to canon.adbTristan Gingold2016-02-171-0/+2
* simul: fix local protected object, boolean for-generate loopTristan Gingold2016-02-143-38/+51
* simul debugger: handle more concurrent statements.Tristan Gingold2016-02-141-0/+50
* simul: more fixes for std_ulogic.Tristan Gingold2016-02-142-17/+21
* psl: cover directive works on a sequence, not on a property.Tristan Gingold2016-02-1416-78/+292
* simul: preliminary work to support PSL.Tristan Gingold2016-02-147-105/+323
* PSL: move canon code to canon.adbTristan Gingold2016-02-147-135/+308
* simul: return the exit status set by std.envTristan Gingold2016-02-141-2/+4
* simul: check for no unconstrained port/generic of top-level entity.Tristan Gingold2016-02-142-1/+30
* simul: make delayed signal elaborated.Tristan Gingold2016-02-101-0/+1
* simul: add support of e8.Tristan Gingold2016-02-109-170/+205
* simul: handle generic override.Tristan Gingold2016-02-103-20/+106
* evaluation: handle whitespace for 'value.Tristan Gingold2016-02-103-1/+54
* build_enumeration_value: correctly handle characters.Tristan Gingold2016-02-101-12/+22
* simul: handle slice in individual association for subprograms.Tristan Gingold2016-02-101-0/+11
* simul: fix type conversion to unconstrained array.Tristan Gingold2016-02-101-14/+35
* simul: fix corner cases for image.Tristan Gingold2016-02-101-100/+131
* simul: fix issue14.Tristan Gingold2016-02-101-10/+21
* simul: fix elaboration check for implicit signals.Tristan Gingold2016-02-101-0/+1
* simul: fix individual association for array.Tristan Gingold2016-02-091-3/+4
* simul: add missing canon.Tristan Gingold2016-02-091-3/+3
* simul: avoid stupid crashes in debugger.Tristan Gingold2016-02-091-2/+10
* PSL: handle and/or in boolean assertion.Tristan Gingold2016-02-093-19/+66
* Improve mixed dump of PSL and VHDL nodes.Tristan Gingold2016-02-092-14/+16
* A subtype of a resolved array type is resolved.Tristan Gingold2016-02-061-0/+3
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