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* synth: file support (WIP).Tristan Gingold2019-11-121-1/+2
* synth: initial support for file types. For #1004Tristan Gingold2019-11-111-27/+33
* synth: initial support of access type. For #1004Tristan Gingold2019-11-111-0/+4
* vhdl-ieee-std_logic_1164: minor simplification.Tristan Gingold2019-11-061-21/+8
* synth: handle edge operators in synth_predefined_function_call.Tristan Gingold2019-11-062-5/+4
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-062-6/+15
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-041-1/+2
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-306-200/+216
* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-251-0/+2
* vhdl-canon: handle simple signal assignment in vunits.Tristan Gingold2019-10-251-273/+272
* vhdl-canon: extract canon_concurrent_label.Tristan Gingold2019-10-251-20/+25
* vhdl-annotations: extract annotate_concurrent_statement.Tristan Gingold2019-10-251-47/+53
* vhdl-annotations: minor renaming.Tristan Gingold2019-10-251-8/+8
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-254-119/+122
* vhdl-parse_psl: add comments.Tristan Gingold2019-10-251-8/+71
* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
* vhdl-annotations: handle some declarations in vunits.Tristan Gingold2019-10-231-0/+6
* vhdl-canon: handle some declarations in vunits.Tristan Gingold2019-10-231-2/+18
* vhdl-sem_psl: analyze some declarations.Tristan Gingold2019-10-231-0/+18
* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-235-14/+31
* vhdl-sem_decls: extract sem_declaration.Tristan Gingold2019-10-231-121/+118
* vhdl-sem_decls: add comment.Tristan Gingold2019-10-211-0/+3
* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
* psl: add active state.Tristan Gingold2019-10-211-0/+7
* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
* vhdl: try to convert identifier to token only for identifiersTristan Gingold2019-10-201-1/+3
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-164-11/+65
* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-151-0/+7
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-154-1/+15
* vhdl-evaluation: handle bit condition operator. Fix #977Tristan Gingold2019-10-131-0/+3
* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-132-0/+7
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-112-18/+30
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-114-14/+64
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-112-0/+15
* vhdl: do not try to recognize mentor version of std_logic_arith.Tristan Gingold2019-10-101-0/+7
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-104-1/+201
* synth: handle package bodies.Tristan Gingold2019-10-071-0/+1
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-072-81/+74
* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-071-1/+2
* Rework errors handling, to have a more generic framework.Tristan Gingold2019-10-062-4/+61
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-011-13/+8
* vhdl: recognize div operators.Tristan Gingold2019-09-302-0/+27
* vhdl-std_package: reduce cascaded error messages.Tristan Gingold2019-09-301-0/+1
* vhdl: recognize rotate functions.Tristan Gingold2019-09-222-0/+17