iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	2	-47/+70
*	vhdl: linearize analyze and evaluation of concat operators.	Tristan Gingold	2019-07-26	5	-360/+647
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	2	-1/+13
*	vhdl: handle (discard) more pragmas.	Tristan Gingold	2019-07-25	1	-0/+8
*	vhdl annotations: fix annotation of type in interface list.	Tristan Gingold	2019-07-24	1	-0/+1
*	vhdl scanner: handle pragma translate_on/translate_off.	Tristan Gingold	2019-07-24	2	-4/+98
*	vhdl: recognize resize function.	Tristan Gingold	2019-07-24	2	-0/+38
*	vhdl-prints: improve output for ports/generics.	Tristan Gingold	2019-07-22	1	-5/+27
*	synth: minor rework.	Tristan Gingold	2019-07-22	2	-0/+14
*	synth: initial support for for-generate statement.	Tristan Gingold	2019-07-20	1	-5/+8
*	vhdl: add a comment.	Tristan Gingold	2019-07-16	1	-0/+3
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	2	-0/+68
*	vhdl: avoid a crash on no matching operator error.	Tristan Gingold	2019-07-15	1	-1/+7
*	vhdl-sem_names: avoid a crash on parenthesis of	Tristan Gingold	2019-07-15	1	-2/+2
*	find_top_entity: avoid crash on missing entity, handle	Tristan Gingold	2019-07-15	2	-13/+27
*	ghdlsynth: check top entity can be a top entity.	Tristan Gingold	2019-07-14	3	-4/+6
*	vhdl: refactoring: remove configure function with string access.	Tristan Gingold	2019-07-14	4	-29/+14
*	vhdl: set location on reference to the anonymous signal declaration.	Tristan Gingold	2019-07-14	1	-0/+1
*	vhdl: fixes in find_top_entity (handle for-generate, remove early return)	Tristan Gingold	2019-07-14	2	-5/+27
*	vhdl: cleanup in clear_instantiation_configuration.	Tristan Gingold	2019-07-13	4	-70/+23
*	simul-elaboration: rewrite assertion.	Tristan Gingold	2019-07-13	1	-3/+3
*	vhdl-configuration: improve error message.	Tristan Gingold	2019-07-11	1	-1/+1
*	vhdl: minor reformating.	Tristan Gingold	2019-07-11	2	-8/+5
*	vhdl-sem_lib: save and restore nbr_errors in	Tristan Gingold	2019-07-11	1	-0/+10
*	libghdl: import Free_Dependence_List.	Tristan Gingold	2019-07-11	2	-0/+4
*	vhdl-nodes: add comments	Tristan Gingold	2019-07-11	1	-0/+16
*	synth: do not crash on use of std_logic_1164 2008.	Tristan Gingold	2019-07-10	1	-10/+4
*	vhdl: improve an error message.	Tristan Gingold	2019-07-10	1	-1/+1
*	vhdl-sem_lib: Load_Parse_Design_Unit: ignore checksum if	Tristan Gingold	2019-07-09	1	-3/+6
*	vhdl-sem_lib: free_dependencies: only free entity aspect.	Tristan Gingold	2019-07-09	1	-3/+19
*	libghdl: automatically set the prefix from shared library	Tristan Gingold	2019-07-09	2	-0/+8
*	vhdl: report an error in case of missing binding indication in config spec.	Tristan Gingold	2019-07-09	1	-11/+21
*	vhdl simul-elaboration: minor rewrite.	Tristan Gingold	2019-07-08	1	-3/+1
*	vhdl-annotations: partial revert of previous patch for	Tristan Gingold	2019-07-04	1	-0/+10
*	synth: handle some "/=".	Tristan Gingold	2019-07-04	1	-0/+20
*	vhdl/translate: reindent.	Tristan Gingold	2019-07-04	1	-1/+1
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	17	-57/+57
*	parse: improve error message for incorrect use of '!'.	Tristan Gingold	2019-07-04	1	-0/+4
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	16	-109/+257
*	Move pnodes.py.py to xtools directory.	Tristan Gingold	2019-07-04	1	-1/+1
*	synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.	Tristan Gingold	2019-07-04	1	-2/+2
*	vhdl: translate anonymous_signal_declaration.	Tristan Gingold	2019-07-03	4	-9/+8
*	vhdl: avoid a crash on label parenthesis.	Tristan Gingold	2019-07-03	1	-0/+1
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	18	-186/+384
*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	1	-1/+2
*	vhdl: adjust python pathes in Makefile.	Tristan Gingold	2019-07-02	1	-9/+11
*	vhdl: improve error message.	Tristan Gingold	2019-07-01	1	-2/+1
*	vhdl: recognize more predefined std_logic_unsigned functions.	Tristan Gingold	2019-06-30	2	-0/+24
*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	2	-0/+15
*	vhdl: recognize std_logic_unsigned	Tristan Gingold	2019-06-29	4	-1/+155