aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl
Commit message (Expand)AuthorAgeFilesLines
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-057-271/+362
* vhdl-prints: avoid assertion on empty hbox for simple loopTristan Gingold2021-01-041-7/+16
* vhdl: recognize ieee.numeric_std_unsigned. For #1572Tristan Gingold2021-01-014-1/+136
* trans-chap3: also compute the size of record constraints for unbounded subtypesTristan Gingold2020-12-311-2/+23
* vhdl: improve error message for invalid record element constraint.Tristan Gingold2020-12-311-1/+1
* Rework initialization and finalization.Tristan Gingold2020-12-304-4/+16
* trans-chap3: compute size of subelements for unconstrained parent subtypesTristan Gingold2020-12-291-8/+39
* scripts: move 'pyGHDL/xtools' to 'scripts', update Makefiles and docs accordi...umarcor2020-12-281-15/+20
* libraries: Load_Std_Library: now return a status.Tristan Gingold2020-12-263-6/+34
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-088-279/+348
* vhdl: recognize logica vec/log and log/vec operators. For #1520Tristan Gingold2020-12-032-0/+96
* vhdl-sem_stmts: fix typo (#1518)Douwe den Blanken2020-11-201-1/+1
* vhdl-parse: improve error recovery on extra right parenthesisTristan Gingold2020-11-041-7/+21
* vhdl-parse: improve error recovery on tick.Tristan Gingold2020-11-041-0/+5
* vhdl-parse: do not skip token in case of error. Fix #1500Tristan Gingold2020-10-291-1/+1
* vhdl-sem_scopes: avoid a crash on invalid selected name. Fix #1490Tristan Gingold2020-10-101-0/+4
* vhdl-parse: improve error message for extra '('.Tristan Gingold2020-10-091-1/+5
* vhdl-sem_specs: avoid noisy error messageTristan Gingold2020-10-071-3/+6
* vhdl-sem_decls: avoid a crash after a parse error.Tristan Gingold2020-10-071-4/+11
* vhdl-sem_types: improve error handling on index subtypes. Fix #1473Tristan Gingold2020-09-291-3/+7
* vhdl-sem_psl: fix crash in case of error in assert statement. Fix #1480Tristan Gingold2020-09-281-2/+5
* vhdl-canon: canon generic associations for subprogram instantiations.Tristan Gingold2020-09-281-1/+6
* vhdl-sem_expr: evaluate operands only if the operator result is not static.Tristan Gingold2020-09-281-5/+13
* vhdl-evaluation: minor rewrite.Tristan Gingold2020-09-281-5/+5
* vhdl: evaluate operands of operators, check bounds. For #1475Tristan Gingold2020-09-262-14/+30
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-2611-217/+390
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-249-287/+495
* vhdl-sem_types: fix staticness of 'open' array constraint. Fix #1469Tristan Gingold2020-09-211-0/+1
* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-162-0/+36
* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-142-0/+68
* vhdl: allow conflict design unit name with -frelaxedTristan Gingold2020-09-122-17/+43
* sem_parenthesis_name: handle more error cases.Tristan Gingold2020-09-061-1/+5
* vhdl: sem_parenthesis_name: do not crash on any type attribute. Fix #1456Tristan Gingold2020-09-061-18/+19
* trans-rtis: adjust max_depth of records. For #1404Tristan Gingold2020-08-261-3/+7
* vhdl/translate: handle vhdl-93 'last_value. Fix #1440Tristan Gingold2020-08-266-75/+207
* vhdl-evaluation: make eval_dyadic_bit_array_operator more generic.Tristan Gingold2020-08-251-42/+71
* vhdl-sem_names: check name staticness of signal attributes. Fix #1412Tristan Gingold2020-08-081-58/+79
* vhdl-canon: minor cleanup.Tristan Gingold2020-08-082-61/+0
* vhdl: renaming in vhdl-canon.Tristan Gingold2020-08-085-188/+202
* vhdl: recognize more operators for std_logic_unsigned/signed.Tristan Gingold2020-08-072-32/+128
* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-072-25/+116
* trans-chap6: fix reuse violation of a node.Tristan Gingold2020-08-061-0/+1
* vhdl-sem_names: use element type of prefix type for indexed names.Tristan Gingold2020-08-052-10/+16
* translate: minor changes.Tristan Gingold2020-08-043-4/+2
* vhdl: handle force/release statements in translate and grt. For #1416Tristan Gingold2020-08-033-18/+205
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-0118-112/+624
* vhdl: add force and release tokens. For #1416Tristan Gingold2020-08-012-0/+6
* translate: add a function to get allocation kind of layout var.Tristan Gingold2020-07-293-1/+15
* trans-chap6: adjust types in translate_selected_element.Tristan Gingold2020-07-281-24/+28
* trans-chap8: avoid to create slice type too late.Tristan Gingold2020-07-281-0/+10