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* synth: handle package bodies.Tristan Gingold2019-10-077-9/+70
* synth-oper: handle to_bitvector, simplify.Tristan Gingold2019-10-071-9/+18
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-074-84/+79
* ghdlsynth: setup error messages for netlists.Tristan Gingold2019-10-071-0/+2
* synth-disp_vhdl: handle enum of width 1 forTristan Gingold2019-10-071-2/+6
* synth-oper: add support for more functions.Tristan Gingold2019-10-071-1/+51
* synth: preliminary support for user packages.Tristan Gingold2019-10-074-84/+85
* synth: allow unconnected port.Tristan Gingold2019-10-071-5/+7
* ghdlsynth: add --out=dumpTristan Gingold2019-10-071-1/+7
* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-072-4/+9
* synth: propagate assignments out of subprograms. Fix #960Tristan Gingold2019-10-063-2/+43
* netlists-dump: improve output for --out=rawTristan Gingold2019-10-061-4/+5
* synth: revert patch on synth_subprogram_association.Tristan Gingold2019-10-063-8/+4
* synth: handle subtypes in components. Fix #970Tristan Gingold2019-10-064-20/+61
* ghdlsynth: fix crash when using libghdl.Tristan Gingold2019-10-063-3/+5
* synth: fix crash for port subtype in component.Tristan Gingold2019-10-061-1/+1
* synth: handle /= with non-matching length. For #968Tristan Gingold2019-10-061-6/+10
* netlists: remove get_parent for instance.Tristan Gingold2019-10-061-2/+0
* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-065-6/+5
* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-0612-33/+34
* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-064-9/+8
* netlists: Remove Get_Name renaming for instances.Tristan Gingold2019-10-065-10/+9
* synth: handle neg for integers.Tristan Gingold2019-10-061-0/+13
* synth: add error messages for latches.Tristan Gingold2019-10-066-6/+198
* netlists-dump: add prefix to numbers.Tristan Gingold2019-10-061-8/+8
* errorout: reserve eargs for synthesis.Tristan Gingold2019-10-062-1/+21
* Rework errors handling, to have a more generic framework.Tristan Gingold2019-10-065-206/+239
* synth: fix selected signal assignment (use basetype).Tristan Gingold2019-10-051-1/+1
* synth: add support for comp. equal of two numeric signed (#966)T. Meissner2019-10-051-0/+4
* synth: support block declarations.Tristan Gingold2019-10-051-2/+16
* synth: minimal support for blocks. Fix #965Tristan Gingold2019-10-052-0/+19
* netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.Tristan Gingold2019-10-041-0/+18
* netlists-disp_vhdl: add qualification when needed for =Tristan Gingold2019-10-041-5/+24
* netlists-disp_vhdl: handle empty operand for concat2, addTristan Gingold2019-10-041-1/+30
* netlists-disp_vhdl: handle id_negTristan Gingold2019-10-041-0/+2
* synth: preliminary work to support procedure calls.Tristan Gingold2019-10-041-118/+200
* synth: factorize code to read memories.Tristan Gingold2019-10-043-74/+47
* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-10-031-1/+1
* synth-oper: convert type of unary operation operand.Tristan Gingold2019-10-033-4/+12
* synth: factorize code for synth_target.Tristan Gingold2019-10-031-86/+24
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-035-13/+13
* synth: remove unused wlen field of bound_type.Tristan Gingold2019-10-034-10/+1
* synth-inference: minor improvement.Tristan Gingold2019-10-031-10/+9
* synth-inference: fix handling of reset/preset chains inTristan Gingold2019-10-031-3/+7
* synth-oper: handle non-constant integer divisions.Tristan Gingold2019-10-031-2/+1
* synth-context: slightly relax assertion.Tristan Gingold2019-10-031-1/+12
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-038-58/+115
* synth: rework synth_target.Tristan Gingold2019-10-021-26/+19
* synth: simplify dyn_insert.Tristan Gingold2019-10-025-18/+11
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-025-22/+9
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