testsuite/gna/bug0117/repro3.vhdl


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entity repro3 is
end;

architecture behav of repro3 is
  type rec1 is record
    wr : bit;
    dat : bit_vector(7 downto 0);
  end record;

  signal s : rec1;
begin
  s <= ('0', x"01");
end behav;