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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity repro_arith is
end repro_arith;
architecture behav of repro_arith is
signal s : unsigned (7 downto 0) := x"00";
begin
process
begin
s <= s + 1;
wait for 1 ns;
end process;
end behav;
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