blob: 7bcaeea54cf6fe9cdcf7a63b966cbfc415cce1db (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic(
BITS : positive);
port(
input : in unsigned(BITS - 1 downto 0));
end entity;
architecture rtl of ent is
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity;
architecture rtl of test is
constant MAX : positive := 7;
signal input : u_unsigned(MAX - 1 downto 0);
-- constant CONST : unsigned := to_unsigned(MAX, input);
begin
ent : entity work.ent
generic map(
BITS => MAX)
port map(
input => to_unsigned(MAX, input));
--input => CONST);
end architecture;
|
