1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity testbench is
end entity;
architecture simu of testbench is
-- Dummy control
signal clk : std_ulogic := '0';
signal simu_clock_enable : std_ulogic := '1';
-- Dummy source signal
signal data_src : std_ulogic_vector(1 downto 0) := "00";
-- Three destination signals
signal data_dst1 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst2 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst3 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst4 : std_ulogic_vector(1 downto 0) := "11";
begin
-- Solution 1
-- THIS WORKS
process(all)
variable idx : integer;
begin
for c in 0 to 1 loop
idx := c;
data_dst1(idx) <= data_src(idx);
end loop;
end process;
-- Solution 2
-- FIXME THIS DOES NOT WORK, CREATES XXX
gen2 : for c in 0 to 1 generate
process(all)
variable idx : integer;
begin
idx := c;
data_dst2(idx) <= data_src(idx);
end process;
end generate;
-- Solution 4
-- THIS WORKS
gen4 : for c in 0 to 1 generate
process(all)
constant idx : integer := c;
begin
data_dst4(idx) <= data_src(idx);
end process;
end generate;
-- Solution 3
-- THIS WORKS
gen3 : for c in 0 to 1 generate
constant idx : integer := c;
begin
data_dst3(idx) <= data_src(idx);
end generate;
-- Dummy clock generation
clk <= (not clk) and simu_clock_enable after 5 ns;
-- Main testbench process
process
-- To print simulation messages
variable l : line;
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
write(l, string'("Result 1 : "));
write(l, to_string(data_dst1));
writeline(output, l);
write(l, string'("Result 2 : "));
write(l, to_string(data_dst2));
writeline(output, l);
write(l, string'("Result 3 : "));
write(l, to_string(data_dst3));
writeline(output, l);
write(l, string'("Result 4 : "));
write(l, to_string(data_dst4));
writeline(output, l);
simu_clock_enable <= '0';
end process;
end architecture;
|
