testsuite/gna/issue1257/repro2.vhdl


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entity repro2 is
end repro2;

architecture behav of repro2 is
   signal left : bit_vector(1 downto 0);
begin
    process
    begin
      for i in 1 to 2 loop
        left(i) <= '1';
      end loop;
      wait;
    end process;
end;