testsuite/gna/issue1257/repro3.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

entity repro3 is
  generic (hi : natural := 1);
end repro3;

architecture behav of repro3 is
   signal left : bit_vector(hi downto 0);
begin
    process
    begin
      for i in 1 to 2 loop
        left(i) <= '1';
      end loop;
      wait;
    end process;
end;