testsuite/gna/issue1684/repro.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

entity repro is
end;

architecture behav of repro is
  signal count : natural;

  procedure proc (signal cnt : inout natural;
                  signal inp : bit_vector (3 downto 0)) is
  begin
    report "proc executed";
    if inp'event then
      cnt <= cnt + 1;
    end if;
  end proc;

  signal s : bit_vector (3 downto 0);
begin
  proc (count, inp (3 downto 0) => s);

  process
  begin
    wait for 1 ns;
    s <= x"3";
    wait for 1 ns;
    s <= x"b";
    wait for 1 ns;
    assert count = 2 severity failure;
    wait;
  end process;
end behav;